By: Dan Ganousis, Codasip
I had the privilege of being a co-presenter with Vijay Subramaniam, Head of IC Design at Microsemi, at this year’s Design Automation Conference in Austin, TX. Our presentation was regarding the benefits Vijay’s group achieved from optimizing the Codasip Bk-3 RISC-V processor core. If you’d like to view the presentation slides, they can be found here.
A nice summary of the Microsemi results are shown on a table on slide 9, and shown here:
In row 1 of the table are the results of a DSP function using the off-the-shelf configuration of the Codasip 3-stage RISC-V processor. The second row shows the performance improvement gained by adding a serial multiplier, while row 3 shows the performance using a parallel multiplier. Where the benefits become very interesting is in row 4 where Microsemi has added DSP extensions to the RISC-V ISA – notice the improvement in performance is over 56x the off-the-shelf version of the same processor.
What makes these results impressive is that they were achieved in a couple of days – not the many months it would take to manually modify the RTL and SDK. Codasip employs a model-based high-level design methodology that allows their users to make these fast IP modifications to accurately explore the design space of their processor implementation.
This is an excellent example of how combining RISC-V processor IP with high-level EDA tools yields meaningful improvements in processor performance by optimizing at the ISA level. It’s worth checking out how Codasip’s RISC-V processor IP and Studio tool set can benefit you too.