Codasip to present at <i>Mentor Forums for Emulation</i> in India

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Hyderabad, India | 10 October, 2017
Bangalore, India | 12 October, 2017

As the verification and validation requirements for modern systems become more and more complex, hardware emulation with its versatility becomes the methodology to go to. At Mentor Forums for Emulation 2017, this shift in emulation usage will be explained and discussed through a number of talks by highly relevant presenters, and Codasip  as Mentor’s trusted partner  will be one of them.

Mentor, the organizer of the Mentor Forums for Emulation summit, offers a wide variety of IP design technologies, and is a leading provider of tools for functional verification. Codasip, a founding member of the RISC-V Foundation, develops its own RISC-V cores, and is the first vendor to provide unique software tools for customization and optimization of their cores. RISC-V is a new open-standard ISA which is highly flexible, customizable, and extensible.

The partnership of Mentor and Codasip enabled experts of both companies to join forces and develop a way of verifying Codasip’s RISC-V processors directly in the hardware environment of Mentor’s Veloce® emulator. This resulted in a rather impressive acceleration of the verification process: from four times faster verification with a testbench and SV pipes, to 25.6 times when using UVM, FlexMem, and an external reference model:

Codasip will reveal the details of this achievement at the Mentor Forums. This year, the event will consist of two parts, one taking place on October 10th in Hyderabad, and the other on October 12th in Bangalore, India; Codasip is featured on both days. The talks will be delivered by Codasip’s VPs Marcela Zachariášová, Head of Verification, and Michal Kajan, Head of IP.

Mentor Forums for Emulation India 2017 official webpage
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About Codasip
About RISC-V