Using Questa® SLEC to Speed Up Verification of Multiple HDL Outputs

Whitepaper

Questa® SLEC, the formal analysis app from Mentor, was designed to automatically compare a block of code (“specification” RTL) with its functional equivalent that has been slightly modified (“implementation” RTL), helping design teams save considerable amounts of time and resources.

Codasip, the leading provider of configurable RISC-V® IP, has come up with a new use of this tool: the verification team uses it to compare a fully UVM-verified HDL code, for example Verilog, with a new HDL output, such as SystemVerilog or VHDL, making sure that they are functionally identical – in a fraction of the time needed before. Total time required for full verification of a new processor design is then reduced by up to 66%, depending on the desired number of HDL outputs.