We’re exhibiting at Embedded World 2023. Book a meeting with us.

Single unified toolchain empowering processor research


May 23, 2022

The RISC-V’s open Instruction Set Architecture (ISA) has spurred the innovation of free software tools and application software. Many of these software developments are software “islands” that must be combined through scripts. With different tools from different sources, continual interoperability is at risk and there is a support cost of monitoring and updating their interoperability. The alternative is a single unified toolchain. The benefit of the unified approach is twofold. First, the obvious case in that the toolchain upgrades are validated before releases ensuring a functional toolchain reducing or eliminating the required monitoring of different tools and upgrading required scripts. The second benefit is not as obvious but may be the most important: through a single unified toolchain, researchers benefit from enhanced tools.

The Codasip’s University Program makes available Codasip Studio, a single unified for processor architecture’s ISA specifications, development of the processor’s hardware architecture, software development tools, to outputting RTL such as Verilog for FPGA and ASIC synthesis. The University Program has been developed to spur innovation in research and student curriculum. Let’s see, in this blog post, how Codasip Studio will benefit researchers and engineering students.

Single unified toolchain for processor development

Codasip Studio outputs a Hardware Development Kit (HDK) and a Software Development Kit (SDK).  The HDK includes all the tools and tasks to specify a processor’s Instruction Accurate (IA) model and implement it as a Cycle Accurate (CA) model.  These models are specified using CodAL, a C-like processor description language that enables high-level synthesis description of both the IA and CA models. The SDK includes all the tools required for software application development starting at the assembler to linker, to C-compiler, to C-libraries, through software simulator.

As the status of these integrated development tools is aware of each other, as in a makefile software build, only the required tasks are built. For example, if you modify a file that changes the IA model and is shared with the CA model, all the tasks for both the IA and CA model will be marked as not built. Upon requesting a higher-level task to be built, all lower dependent tasks that are not built will be built first. A good example is the SDK (IA) task.  If this task is built, all dependent tasks such as Model Compilation, Assembler, Disassembler, Profiler, Simulator, Debugger, C/C++ compiler, and SDK libraries will be built if necessary. No script development or toolchain maintenance required.

Enhanced tools through a Unified Toolchain

How can Codasip Studio’s unified toolchain enhance research?  Tightly coupling application integration with program acceleration into a processor’s core is a new research domain. To make engineering decisions, data is required. Codasip Studio’s integrated Profiler can analyze a software application to determine where clock cycles are spent, enabling researchers to focus where new instructions can result in program acceleration through cycle count reduction.

Snapshot of Codasip Studio

As in this example, the profiler annotates the C-program to highlight where clock cycles are spent, and the associated assembly sequence. The Researchers can minimize the original sequence into a single new instruction with the objective of not elongating the clock period.

RISC-V generated compiler realizes instruction acceleration

Creating new instructions for acceleration remains in the hypothetical sphere until it can be incorporated into useful applications. Codasip Studio compiler’s input is the processor’s IA model.  Analyzing data from the profiler, researchers define a new instruction into the processor’s ISA, and upon rebuilding the SDK (IA), a compiler will be aware of the new instruction and use it in subsequent program builds.

From the program disassembly above, the newly added instruction has been incorporated into the compiler to replace the original two RISC-V instructions. Application acceleration has been achieved through cycle count reduction. The program cycle count can also be verified through running the updated program through the Profiler.

The entire process from initial application profiling, minimizing the instructions, to implementing a new instruction into the IA and CA models, and verification of program cycle count reduction can be achieved in an hour or two. The unified toolchain enables a very tight loop from data to concept to experimentation. With these short development cycles, researchers can easily experiment to find the optimal solution.

Get started with the University Program to explore Codasip Studio’s unified toolchain and how it can benefit your research in Program Security, Functional Safety, Artificial Intelligence, Real-Time Embedded Systems and other Domain Specific Architectures.

Learn more about the Codasip University Program

Keith Graham

Related Posts

Check out the latest news, posts, papers, videos, and more!

Being a design verification engineer is fun and rewarding

November 21, 2022
By Lauranne Choquin

design automation to drive innovation and differentiation

July 7, 2022
By Lauranne Choquin

architecture optimization for university researchers

May 2, 2022
By Keith Graham

architecture optimization for university researchers


May 2, 2022

With closed processor Instruction Set Architectures (ISA) with limited access to processor Intellectual Property (Arm and x86), university professors have often limited their research to two main spheres: optimizing software algorithm(s) and external hardware. University researchers have not been able to consider optimizing the processor due to the lack of access to processor Intellectual Property (IP).   Where these two spheres overlap, trade-offs are made to optimize the solution. A conventional research barrier is the exclusion of processor architecture optimization. Coprocessors or external accelerators can be explored, but they are limited and costly in solving tomorrow’s technological challenges in Processor Security, Functional Safety, Intelligent Memories, and Artificial Intelligence.

We launched the Codasip University Program in March 2022 to support you, engineering professors and students, and advance technology that will solve tomorrow’s technological challenges. Because of Moore’s Law and Dennard’s Scaling challenges, computer architects have developed solutions through integrating multiple homogenous and heterogenous cores. Tightly coupling application acceleration and application-specific requirements into the processor core is a new research domain to solve tomorrow’s computational needs. Let see, in this blog post, how you can jump start on this opportunity with our program.

University research is often limited to hardware and software optimization

Conventional research has been limited to software algorithms and external hardware resources due to fixed and closed processor architectures. Unfortunately, an important component of the research equation – the processor – has been left out.

Processor architecture optimization is excluded from university research

Let’s start with an example. Sequential memory elements such as register files and pipeline registers are not commonly protected against single bit upsets that may occur via an alpha particle or a security attack. To protect from these upsets, external processor monitors or a 1 out of 2 voting strategy can be considered, but greatly increasing the design and validation complexity at increased cost.

Optimizing the processor architecture itself is missing from the above solutions. Three elements are now available to you through the Codasip University Program to break through this barrier and to include tightly coupling the application’s requirements into the processor.

RISC-V and Codasip Studio made available to university researchers to break through the processor architecture optimization barrier

With access to RISC-V cores and Codasip Studio, you, university researchers and students, can now explore new processor architectures that integrate application-specific features and acceleration – and ultimately become tomorrow’s solutions and engineers.

Breaking through the research barrier to include processor architecture optimization

With RISC-V IP and Codasip Studio, resources can now be brought into the processor for optimization and solution trade-offs can occur between all three spheres.

Processor architecture optimization included in university research

Continuing our single bit upset example, can we solve this fault by integrating a solution into the processor to protect its memory and register bits?

Architectural optimization through application-specific integration into the core

Processor architecture optimization involves two key concepts:  tightly coupling application-specific functionality into the processor and enhancing the processor performance through cycle-count reduction.

Using Codasip Studio and RISC-V cores, you can add Hamming encoding to write to the register file and decoding upon reads. The register file is now protected through two-bit error detection and single-bit error correction (ECC) by developing functions in the processor’s Cycle Accurate (CA) model using CodAL.

CodAL is an architectural high-level description language that describes the processor’s ISA (Instruction Accurate (IA) model) and the hardware implementation (Cycle Accurate (CA) models). Pipeline registers can be protected with parity to provide real-time bit error detection. When a fault is detected, the parity checker can assert a processor exception for handling. ECC and parity can be extended to either the L1 or L2 caches.

For a set of applications, would integrating the processor into solving single bit upsets reduce design complexity, development and validation time, as well as solution cost? Applications can be accelerated by reducing program clock cycles assuming the clock frequency remains constant. Using Codasip Studio’s profiler, you can analyze the most common sequence of operations to replace two or more RISC-V instructions with a single new instruction. Using CodAL to update both the IA and CA models, this new instruction becomes available to the application developer through Codasip Studio’s assembler and C-compiler.

Explore new research avenues with the Codasip University Program

Empowering processor architecture optimization enables you to imagine new avenues of research that was not feasible before. Here are just three possibilities…

Empowering processor architecture optimization brings new possibilities for researchers

Get started with the Codasip University Program to explore new processor architecture optimizations through integrating application-specific functionality and acceleration.

Keith Graham

Related Posts

Check out the latest news, posts, papers, videos, and more!

5 things I will remember from the 2022 RISC-V Summit

December 22, 2022
By Lauranne Choquin

Being a design verification engineer is fun and rewarding

November 21, 2022
By Lauranne Choquin

How to reduce the risk when making the shift to RISC-V

November 17, 2022
By Lauranne Choquin