Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

Codasip Presence at Upcoming Events: China Roadshow, DAC 2019, and RISC-V Workshop Zurich


May 6, 2019

Munich, Germany – May 6th, 2019 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, is going to be featured at three major industry events around the globe in the second quarter of 2019: China Roadshow 2019, Design Automation Conference in Las Vegas, and RISC-V Workshop in Zurich.

 “Getting Started with RISC-V” Roadshow 2019, May 6–16, is a series of events taking place in five cities across China in eleven days. The show aims to present entry-level examples of innovative RISC-V solutions, and attendance is free of charge. Codasip is co-sponsoring the event and will have Tina Xiang, China General Manager, speaking about Codasip’s smart solutions and tools for automated generation and customization of RISC-V processors. Tina’s presentation starts at 10:00 each day of the main show schedule:

  • Wednesday, May 8, Sheraton Chengdu Lido Hotel
  • Monday, May 13, Hyatt on the Bund, Shanghai
  • Tuesday, May 14, JW Marriott Hotel Hangzhou
  • Thursday, May 16, Crowne Plaza Zhongguancun Beijing

More information about the RISC-V Roadshow China is available on the official event website.

Design Automation Conference 2019, June 2–6 at the Las Vegas Convention Centre in Las Vegas, Nevada, is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and intellectual property (IP). The event will offer close to 300 technical presentations, training sessions, workshops, and an exhibition area featuring of around 200 companies. Codasip’s VP of Worldwide Sales, Jerry Ardizzone, will be presenting his views on the future commercial success of open ISAs as a guest of a panel discussion on Tuesday, June 04, at 10:30. Detailed information on the discussion topic is available on the official DAC 2019 website.

RISC-V Workshop Zurich, June 11–13 at ETH Zurich (Swiss Federal Institute of Technology), is organized by the RISC-V Foundation and again co-sponsored by Codasip. The presentation will be given by Zdeněk Přikryl, Codasip CTO, who will explain the benefits of the open source compiler technologies developed within the LLVM project, and how Codasip integrates the LLDB debugger in its automated toolchain. His presentation is scheduled for Wednesday, June 12, at 17:40. More information about the presentation is available on the official RISC-V Workshop website.

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About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and

GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. For more information about Codasip’s products and services, visit www.codasip.com.

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. For more information about RISC-V, visit www.riscv.org.

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Codasip Studio and Codasip CodeSpace 8.0 available


March 26, 2019

Codasip is pleased to announce the availability of Codasip Studio and Codasip CodeSpace 8.0.0.

Key features of this release:

  • Introduction of a new Codasip Bus Protocol (CPB)
  • Integration of LLDB
  • Integration of OpenOCD

Full changelog is available at: https://support.codasip.com/​downloads/​changelog/

The release is available in the Downloads section of our website:
https://support.codasip.com/​downloads/​software/

Any feedback on this release is welcome. Share it with us on feedback@codasip.com

Kava

Codasip to Demonstrate Technology Leadership and Commitment to Open Standards at Taiwan RISC-V Workshop


March 7, 2019

Munich, Germany – March 7th 2019 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, will address the topics of RISC-V C compiler optimizations and frameworks for ISA compliance in two presentations at the upcoming RISC-V Workshop in Taiwan.

In the first presentation, Codasip CTO Zdeněk Přikryl will demonstrate how Codasip generates and optimizes the latest LLVM version 7.0.1 toolchain to make use of custom instructions, including debugging and profiling. The LLVM project continues to expand rapidly as industry leaders have chosen to adopt LLVM compiler due to its excellent quality of results. While many employ various components of the LLVM toolchain, Codasip has announced availability of LLVM for compilation, code generation, and debugging for its family of RISC-V processors. Full support for LLDB in command-line mode or as part of an Eclipse-based graphical debug is now part of its latest generation of licensable software development tools.

In the second presentation, Codasip engineer Milan Skála will discuss requirements for a RISC-V compliance test framework that could be employed for any valid implementation of the RISC-V standard. He will show Codasip’s methodology as an example. Based on Python’s pytest, it provides golden reference model configuration, including test suite builds along with test suite parametrization, compilation, run control with results evaluation, and compliance test reports.

Karel Masařík, Codasip’s founder and CEO, said: “By addressing the topics of compiler optimizations and ISA compliance testing, Codasip is emphasizing its commitment to open standards for embedded processors. We are dedicated to making meaningful contributions to the RISC-V community to ensure that the ecosystem grows and benefits the entire industry. At the same time, we will of course continue to innovate with our own Codasip Studio which allows for rapid development of optimized and differentiated processor IP.”

The RISC-V Workshop Taiwan takes place on 12–13th March 2019 in the Ambassador Hotel, Hsinchu City, Taiwan. More information about registration and agenda can be found at the event webpage: https://tmt.knect365.com/risc-v-workshop-taiwan/

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information, visit www.riscv.org.

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Vidtoo Technology Licenses Codasip’s Bk3 RISC‑V Processor for High‑Performance Computing SoC


December 17, 2018

Munich, Germany – December 17th 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, announced today that Vidtoo Technology, a leader in semiconductor products for machine learning and high-performance computing, has selected Codasip’s Bk3 processor for future HPC chips.

Vidtoo Technology, based in Hangzhou, China, focuses on high-bandwidth, high-performance, high-connectivity, artificial intelligence platforms and inference engines for data centers as well as 3D video processing technologies for industrial IoT applications and SR (Simulated Reality)/MR applications with on-chip decision making capabilities.

“We are pleased to announce our selection of Codasip’s Bk3 processor for our next HPC products. After careful consideration, we determined that Codasip offered the best combination of performance, value and design expansion ability. Those traits, plus best-in-class support and the broad ecosystem that the open RISC-V ISA brings, gave us confidence that Codasip was the right choice,” stated Thomas Hu, CEO of Vidtoo Technologies. “We look forward to a long and successful partnership with Codasip when we strive to provide customers with the optimal design across our product families.”

The Codasip Bk3 processor, based on the RISC-V open instruction set architecture (ISA) definition, features a single 3-stage in-order execution processor pipeline, and offers optional caches, IEEE 1149.1 debug, and industry standard bus interfaces. Further, the Bk3 – like all Codasip RISC-V implementations – is fully configurable and extensible, offering great advantage over traditional, fixed-configuration processor IP cores.

We are delighted that Vidtoo Technology has chosen Codasip to be its provider of RISC-V processor IP,” added Chris Jones, Codasip’s Vice President of Marketing. “Vidtoo is a rising star in the semiconductor industry with an impressive product portfolio that includes cutting-edge machine-learning devices. They have wide-ranging processing needs, and Codasip technology gives them a proven family of processor solutions complete with a comprehensive high-performance software toolchain.”

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information, visit www.riscv.org.

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Mythic Chooses Codasip to Deliver RISC-V Computing in their Revolutionary Neural Network Platform


December 10, 2018

Campbell, California – December 10th 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, announced today that Mythic, a leader in artificial intelligence (AI) computing technology, has selected Codasip’s configurable Bk3 processor and Codasip Studio for future neural networking chips.

Mythic, based in Redwood City, California, and Austin, Texas, will deliver powerful, life-enhancing AI solutions that customers can push into anything, from fitness bands and hearing aids to self-driving cars and security cameras. The solutions are developed on a unique approach to neural network processing. The Mythic Intelligence Processing Unit (IPU), which performs the inference step of deep neural networks inside the same flash memory array which stores the neural network’s weights, delivers huge advantages in performance, cost, and power consumption versus alternative solutions.

“We chose Codasip’s Bk3 RISC-V processor and Codasip Studio for our PCIe-attached IPU deep learning accelerator because it gave us the flexibility to create a truly unique processor that was specific to our needs, while maintaining compliance to the RISC-V standard,” stated Ty Garibay, VP of Hardware Engineering at Mythic. “While we have the expertise to build our own RISC-V processor, we determined that Codasip Studio, with its automatic generation of both verified hardware and fully compatible software toolchain, was a more efficient approach and allowed us to focus on other critical areas of the product development.”

The Codasip Bk3 processor, based on the RISC-V open instruction set architecture (ISA) definition, features a single 3-stage in-order execution processor pipeline and offers optional caches, IEEE 1149.1 debug, branch prediction, and industry standard bus interfaces. Further, the Bk3 – like all Codasip RISC-V implementations – is fully configurable and extensible, offering great advantage over traditional, fixed-configuration processor IP cores.

With Codasip Studio, designers can begin with a high-level description of a RISC-V micro-architectural implementation defined and delivered by Codasip, and then describe their desired architectural and ISA modifications in the CodAL architecture description language, and then automatically synthesize the design’s RTL, testbench, virtual platform models and processor SDK (C/C++ compiler, debugger, profiler, and other parts).  Time that would otherwise be required to maintain a complete SDK and implementation is significantly reduced thanks to the methodology that uses an Instruction Accurate (IA) processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.

We welcome Mythic to the growing roster of customers that are partnering with Codasip to deliver innovative products based on the RISC-V architecture,” stated Chris Jones, Codasip’s Vice President of Marketing. “RISC-V is ideal for machine learning applications, and Mythic will deliver revolutionary products that employ highly optimized Codasip RISC-V cores.”

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

About Mythic

Mythic is accelerating AI that works for everyone. Today, it is difficult, time-consuming and expensive to build and deploy reliable AI. By offering mixed-signal chips with revolutionary power, cost, and performance capabilities, along with easy-to-use software tools, Mythic is removing those limitations and empowering every AI developer. Mythic’s focus is simple: to enable the next great wave of AI innovation.

Mythic is supported by leading venture capital investors including Softbank, DFJ, Lux, and Data Collective. The company has offices in Austin, TX, and Redwood City, CA.  For more information about Mythic, visit www.mythic-ai.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information, visit www.riscv.org.

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Codasip Releases Studio 8, a Breakthrough in RISC-V Automation, and the Bk7 RISC-V Processor Core for Real-Time Computing Applications


December 6, 2018

Munich, Germany – December 6th, 2018 – CodasipGmbH, the leading supplier of RISC-V® embedded processor IP, announced today the latest version of Studio, a suite of tools optimized for the development and verification of RISC-V processors, and the Bk7 processor, the first Codasip RISC-V core optimized for Linux and real-time performance.

“As the RISC-V ISA specification evolves and adds an ever-increasing number of optional architecture extensions, a processor design methodology that allows for both rapid architectural exploration and simplified creation of easily implementable RTL becomes essential,” stated Chris Jones, Vice President of Marketing at Codasip. “What is needed is a high-level processor description language optimized for RISC-V, so Codasip has delivered Studio 8, a comprehensive tools suite for RISC-V processor development.”

With Studio, designers write a high-level description of a processor in CodAL, an architecture description language, and then automatically synthesize the design’s RTL, test bench, virtual platform models, and processor SDK (C/C++ compiler, debugger, profiler, etc.). Time that would otherwise be required to maintain a complete SDK and implementation is significantly reduced thanks to the methodology that uses an Instruction Accurate (IA) processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.

Codasip employs this silicon-proven methodology to create and deliver a broad portfolio of licensable RISC-V processor IP.  Through these product developments, Studio has evolved to make it more suitable for implementing and extending the instruction set of RISC-V cores. The 8th generation of Codasip Studio, just announced, adds significant new functionality and features, making it the most advanced and effective technology on the market for tailoring RISC-V processors to meet chip designers’ application-specific needs. Specifically, Studio 8 includes:

  • Support for LLVM debugger (LLDB) and OpenOCD,
  • LLVM 7.0,
  • Studio/CodeSpace IDEs based on Eclipse Oxygen along with more interactive consoles,
  • improved test suites and verification to better support user-defined RISC-V extensions.

Further, Codasip architects employed Studio to develop the Bk7 processor, the latest RISC-V micro-architecture in the Codasip portfolio.

A 64-bit machine featuring a balanced 7-stage pipeline with branch prediction, optional full MMU with virtual addressing support for operating systems such as Linux, and support for the popular RISC-V standard extensions as well as industry-standard external interfaces, the Bk7 is Codasip’s highest-performance processor to date and is ideal for system-on-chip designers who need the right balance of power and performance.  Also, the Bk7 is fully customizable so architects can easily add additional instructions, registers or interfaces. And as with each member of the Codasip Bk processor family, the Bk7 comes with the following deliverables:

  • Readable Verilog or VHDL RTL along with test benches and synthesis scripts,
  • SDK consisting of LLVM-based compiler, advanced profiling and debugging tools,
  • both cycle-accurate and fast instruction-accurate simulation tools.

Studio 8 and the Bk7 processor are generally available in the first quarter of 2019, with early access to selected customers immediately.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 with research and development located in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. Codasip is currently venture-backed by Credo Ventures, Ventech Capital, Shenzhen Capital, Paua Ventures, and Western Digital.

For more information about Codasip’s products and services, visit codasip.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open-standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information about RISC-V, visit www.riscv.org.[/cs_text][/cs_column][/cs_row][/cs_section][/cs_content]

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Codasip Secures $10M in Series A Financing to Expand RISC-V Processor Technology Offerings


December 4, 2018

Munich, Germany – December 4th, 2018 – Codasip GmbH, the leading supplier of RISC-V® embedded processor IP, announced today that it has raised $10M in a Series A investment round led by private equity firms Ventech Capital of Paris, France, Shenzhen Capital Group Co., Ltd. of Shenzhen, China, Paua Ventures of Berlin, Germany, and strategic investor Western Digital, following the initial investment led by Credo Ventures of Prague, Czech Republic.

This investment will allow Codasip to grow its global sales and support team while expanding its product development efforts to bring best-in-class RISC-V processor intellectual property and optimization tools to customers around the world.

“The RISC-V movement is growing at a rapid pace and transitioning from an era of raising awareness to an era of customer adoption,” stated Christian Claussen, General Partner of Ventech Capital and a board member of Codasip. “Codasip have the tools and expertise developed over the last decade to create a broad portfolio of licensable RISC-V processors and bring them to market. Ventech Capital is confident that Codasip will continue to provide innovative products to the semiconductor industry.”

Martin Fink, Chief Technology Officer at Western Digital, added: “Western Digital is focused on the next generation of innovation to enable new classes of applications like machine learning, AI, and analytics to deliver the possibilities of data. RISC-V offers a platform for innovation unshackled from the proprietary interface of the past, and this freedom allows us to optimize special-purpose computing capabilities targeted at big data and fast data applications.”

Karel Masařík, Codasip’s founder and CEO, said: “We are honored to welcome aboard this global syndicate of investors who share Codasip’s vision of bringing innovative RISC-V-based processors and optimization tools to the world, and we appreciate the continued dedication, commitment, and support of our earlier investors and the current team.

Codasip aims to have the most comprehensive portfolio of RISC-V processor technology in the industry. Codasip Studio allows for rapid processor development and helps customers differentiate their products through processor IP that is tailored to their design and software requirements, and does so with less cost and risk than using general-purpose offerings. Studio dramatically simplifies the process of optimizing a processor, delivers enormous performance improvement to customers, and allows them to build their own unique RISC-V core that is just right for their application.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 with research and development located in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. Codasip is currently venture-backed by Credo Ventures, Ventech Capital, Shenzhen Capital Group Co., Ltd. of Shenzhen, China, Paua Ventures, and Western Digital.

For more information about Codasip’s products and services, visit codasip.com.

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. For more information, visit www.riscv.org.

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Codasip Expands its Global Reach by Signing Channel Partnerships throughout Asia


September 10, 2018

Campbell, California – September 10th 2018 – Codasip, the leading supplier of RISC‑V® embedded processor IP, today announced that it has signed new reseller representative agreements with leading firms in China, Taiwan, Japan, and India.

New strategic partnerships were formed with Shanghai Jiatao, Maojet Technologies of Taiwan, Delphinium Technologies of Bengaluru, India, and Japan Marketing Office to assist Codasip in reaching the rapidly expanding Asia markets.

“Adding these great companies to our partner roster demonstrates our commitment to making Codasip the premier provider of RISC-V processors,” stated Karel Masařík, founder and CEO of Codasip. “RISC-V momentum is growing and we are uniquely positioned for success with a global presence and a strategy of delivering configurable RISC‑V-based products and development tools.”

Codasip aims to have the most comprehensive portfolio of RISC‑V processor IP in the industry, which is achieved by employing the Codasip Studio processor development tools to continually bring new cores to market. The unique toolset also helps customers differentiate their products by automatically tailoring their processor IP to design and software requirements – and it does so with less cost and risk than with using general-purpose components.

Studio dramatically simplifies the process of tailoring a processor solution and delivering potentially enormous performance improvements.  Further, end users can exploit the power of Studio themselves to build their own unique RISC-V processor that is just right for their application.

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
For more information, visit www.riscv.org.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

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Codasip Inks Deal with Delphinium Technologies to Establish India Presence


September 10, 2018

Campbell, California – September 10th 2018 – Codasip, the leading supplier of RISC‑V® embedded processor IP, today announced that it has signed a representative agreement with Delphinium Technologies to establish Codasip’s presence in India.

Delphinium Technologies of Bengaluru, India, is focused on bringing state-of-the-art EDA technologies and IP to the electronics engineering world.

“Indian companies, government-backed research facilities and universities are all heavily invested in the RISC‑V movement,” stated Susheel Kumar, founder and director of Delphinium.  “Codasip’s technology can help these enterprises become more productive as they develop innovative RISC‑V derivatives. We look forward to helping Codasip introduce their RISC-V processors, tools, and design methodology to the India design community.”

India represents a new frontier for processor IP companies like Codasip,” stated Jerry Ardizzone, Vice President of Worldwide Sales at Codasip. “We are uniquely positioned with our configurable RISC‑V-based products and development tools to help jumpstart the growing India processor and semiconductor design communities, and we look to Delphinium to help us establish roots in the market there.”

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
For more information, visit www.riscv.org.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.
For more information about Codasip’s products and services, visit codasip.com.

About Delphinium

For more information about Delphinium, visit www.delphiniumtech.com.

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