More than Moore with Domain-Specific Processors

Blog, News & Docs

The Moore’s law has had remarkably long validity of almost half a century. Today, however, it is ceasing to apply, opening new pressing questions such as: How to make up for the fact that chip size cannot be effectively reduced any more? What is the new way to improve performance? Roddy’s blogpost digs into one of the most promising answers: Core customization. Read on!

Questa SLEC Tool From Mentor, a Siemens Business, to Help Codasip Speed Up Verification of Multiple HDL Outputs

Blog, News & Docs

Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, has selected Questa® SLEC by Mentor for use as part of its comprehensive verification flow. The Codasip verification team expects this will significantly reduce the time needed to ensure logical equivalence of multiple HDL representations of each of its processors.

RISC-V Shows Growing Momentum and Ecosystem at Embedded World 2018

Blog

Embedded World 2018, the international trade fair for embedded systems, took place between February 27th and March 1st in Nuremberg, Germany. This year, the event enjoyed a record number of participants and a strong presence of RISC-V. In 2016, a visitor to Embedded World saw a set of offerings almost identical to the previous decade – the same semiconductor vendors, software development tool companies, system level offerings. The dominant …

Codasip Processors Not Affected by Meltdown and Spectre

Blog

In the light of recent news about grave processor security issues, Meltdown and Spectre, we would like to assure customers and partners that Codasip processors are not subject to these issues. Meltdown and Spectre take advantage of a flaw in so-called speculative execution, a feature that allows for faster execution of code. Meltdown exploits the fact that low-privilege code and high-privilege memory are not separated properly …

Codasip to Present at Events in Japan and California

Blog, News & Docs

Busy October brings many events all over the globe where Codasip will be represented. Apart from Mentor Forums for Emulation in India, Codasip’s VPs and directors will be presenting at the following events. Design Solution Forum Yokohama, Japan | 13 October, 2017 On Friday October 13th, Design Solution Forum will take place in Yokohama, Japan. Codasip’s Director for EMEA Business …

Codasip to present at <i>Mentor Forums for Emulation</i> in India

Blog, News & Docs

Hyderabad, India | 10 October, 2017 Bangalore, India | 12 October, 2017 As the verification and validation requirements for modern systems become more and more complex, hardware emulation with its versatility becomes the methodology to go to. At Mentor Forums for Emulation 2017, this shift in emulation usage will be explained and discussed through a number of talks by highly …

Does RISC-V mean Open Source Processors?

Blog

“So, RISC-V is an Open ISA, that means a RISC-V processor core is Open Source”. This is a statement that I have often heard this year – however, is it true or false? Before answering this, let’s consider the broader issue of whether open standards automatically mean open source. Open standards are widespread in technology. The communication protocols TCP/IP have …