We will keep you posted about our endeavors to make ASICs more accessible.
Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, has selected Questa® SLEC by Mentor for use as part of its comprehensive verification flow. The Codasip verification team expects this will significantly reduce the time needed to ensure logical equivalence of multiple HDL representations of each of its processors.
Embedded World 2018, the international trade fair for embedded systems, took place between February 27th and March 1st in Nuremberg, Germany. This year, the event enjoyed a record number of participants and a strong presence of RISC-V. In 2016, a visitor to Embedded World saw a set of offerings almost identical to the previous decade – the same semiconductor vendors, software development tool companies, system level offerings. The dominant …
Brno, Czech Republic – February 21st 2017 – In the past weeks, Codasip has been not only planning and expanding business, but also hiring and growing in the personnel area. The main focus stays on the headquarters office in Brno where the whole development team is based. With yearly supplies of young talents fresh from universities, an ideal location in …
In the light of recent news about grave processor security issues, Meltdown and Spectre, we would like to assure customers and partners that Codasip processors are not subject to these issues. Meltdown and Spectre take advantage of a flaw in so-called speculative execution, a feature that allows for faster execution of code. Meltdown exploits the fact that low-privilege code and high-privilege memory are not separated properly …
Busy October brings many events all over the globe where Codasip will be represented. Apart from Mentor Forums for Emulation in India, Codasip’s VPs and directors will be presenting at the following events. Design Solution Forum Yokohama, Japan | 13 October, 2017 On Friday October 13th, Design Solution Forum will take place in Yokohama, Japan. Codasip’s Director for EMEA Business …
Hyderabad, India | 10 October, 2017 Bangalore, India | 12 October, 2017 As the verification and validation requirements for modern systems become more and more complex, hardware emulation with its versatility becomes the methodology to go to. At Mentor Forums for Emulation 2017, this shift in emulation usage will be explained and discussed through a number of talks by highly …
“So, RISC-V is an Open ISA, that means a RISC-V processor core is Open Source”. This is a statement that I have often heard this year – however, is it true or false? Before answering this, let’s consider the broader issue of whether open standards automatically mean open source. Open standards are widespread in technology. The communication protocols TCP/IP have …
By: Dan Ganousis, Codasip I had the privilege of being a co-presenter with Vijay Subramaniam, Head of IC Design at Microsemi, at this year’s Design Automation Conference in Austin, TX. Our presentation was regarding the benefits Vijay’s group achieved from optimizing the Codasip Bk-3 RISC-V processor core. If you’d like to view the presentation slides, they can be found here. A …
At this years DAC we had the opportunity to highlight our collaboration with Mentor on RISC-V verification and reuse. To read more about the collaboration, read the online version of the Verification Horizons magazine. https://verificationacademy.com/verification-horizons/june-2017-volume-13-issue-2/automation-and-reuse-in-risc-v-verification-flow
Extensible Processors vs Accelerators – and how RISC-V changes the dynamic If you were to ask any good designer today what is the best architecture for an SoC that needs to manage complex DSP or high bandwidth traffic demands – you will almost always find the recommendation of using one or more off-the-shelf processors, complimented by hardware accelerators to offload …
