Blog

We will keep you posted about our endeavors to make ASICs more accessible.

Does ISA ownership matter? A Tale of Three ISAs

December 22, 2020 Blog, News & Docs

An instruction set architecture (ISA) is crucial to the development of processors and their software ecosystems. Does ISA ownership matter? Let’s consider three proprietary ISAs and their history to find out.

Open Source vs Commercial RISC-V Licensing Models

November 26, 2020 Blog, News & Docs

Everybody is familiar with commercial licensing from traditional processor IP vendors. In discussing RISC-V, there is widespread confusion of terminology with RISC-V often being described as “open source”, often understood as “free”. But what is reality?

When Considering Processor PPA, Don’t Forget the Instruction Memory

November 12, 2020 Blog, News & Docs

The area of any part of a design contributes both to the silicon cost and to the power consumption, but a simplistic following of the “A” in a processor IP vendor’s PPA numbers can be misleading. What do you need to know?

What is needed to support an operating system?

October 15, 2020 Blog, News & Docs

For each embedded product, software developers need to consider whether they need an operating system; and if so, what type of an OS. Operating systems vary considerably and the choice of one for your processor core has important implications. Let us explore them.

What is processor core complexity?

September 10, 2020 Blog, News & Docs

Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power & area) numbers. In theory, they should provide a level playing field for comparing different processor IP cores, but in reality, the situation is more complex. Let us consider performance.

Understanding the Performance of Processor IP Cores

August 20, 2020 Blog, News & Docs

Codasip’s Expanding RISC-V Offering

July 22, 2020 Blog, News & Docs

In the last three months, Codasip’s RISC-V processor offering has expanded considerably. For some years, Codasip has supplied Bk3 and Bk5 RISC-V cores aimed at low- to medium-complexity embedded applications. But recently four additional cores have joined the Codasip RISC-V offering.

What is SweRV Core EH2?

June 4, 2020 Blog, News & Docs

The Moore’s law has had remarkably long validity of almost half a century. Today, however, it is ceasing to apply, opening new pressing questions such as: How to make up for the fact that chip size cannot be effectively reduced any more? What is the new way to improve performance? Roddy’s blogpost digs into one of the most promising answers: Core customization. Read on!

More than Moore with Domain-Specific Processors

May 6, 2020 Blog, News & Docs

The Challenges of Making Open-Source RISC-V Deployment Effective

April 17, 2020 Blog, News & Docs

Using open-source is appealing, but also challenging. Can there be solid support for open core deployment? What will be the “Linux way” in the hardware domain?

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