Blog

We will keep you posted about our endeavors to make ASICs more accessible.

Codasip’s Expanding RISC-V Offering

July 22, 2020 Blog, News & Docs

In the last three months, Codasip’s RISC-V processor offering has expanded considerably. For some years, Codasip has supplied Bk3 and Bk5 RISC-V cores aimed at low- to medium-complexity embedded applications. But recently four additional cores have joined the Codasip RISC-V offering.

What is SweRV Core EH2?

June 4, 2020 Blog, News & Docs

The Moore’s law has had remarkably long validity of almost half a century. Today, however, it is ceasing to apply, opening new pressing questions such as: How to make up for the fact that chip size cannot be effectively reduced any more? What is the new way to improve performance? Roddy’s blogpost digs into one of the most promising answers: Core customization. Read on!

More than Moore with Domain-Specific Processors

May 6, 2020 Blog, News & Docs

The Challenges of Making Open-Source RISC-V Deployment Effective

April 17, 2020 Blog, News & Docs

Using open-source is appealing, but also challenging. Can there be solid support for open core deployment? What will be the “Linux way” in the hardware domain?

Have you checked the hidden costs of deploying an open source RISC-V core?

April 9, 2020 Blog, News & Docs

It is often implied that if you use an open source processor core there are no costs associated with using it. Is that actually true?

Questa SLEC Tool From Mentor, a Siemens Business, to Help Codasip Speed Up Verification of Multiple HDL Outputs

August 19, 2019 Blog, News & Docs

Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, has selected Questa® SLEC by Mentor for use as part of its comprehensive verification flow. The Codasip verification team expects this will significantly reduce the time needed to ensure logical equivalence of multiple HDL representations of each of its processors.

RISC-V Shows Growing Momentum and Ecosystem at Embedded World 2018

March 13, 2018 Blog

Embedded World 2018, the international trade fair for embedded systems, took place between February 27th and March 1st in Nuremberg, Germany. This year, the event enjoyed a record number of participants and a strong presence of RISC-V. In 2016, a visitor to Embedded World saw a set of offerings almost identical to the previous decade – the same semiconductor vendors, software development tool companies, system level offerings. The dominant …

Humans of Codasip: the Hiring Efforts and an Office Photo Shoot

February 21, 2018 Blog

Brno, Czech Republic – February 21st 2017 – In the past weeks, Codasip has been not only planning and expanding business, but also hiring and growing in the personnel area. The main focus stays on the headquarters office in Brno where the whole development team is based. With yearly supplies of young talents fresh from universities, an ideal location in …

Codasip Processors Not Affected by Meltdown and Spectre

January 10, 2018 Blog

In the light of recent news about grave processor security issues, Meltdown and Spectre, we would like to assure customers and partners that Codasip processors are not subject to these issues. Meltdown and Spectre take advantage of a flaw in so-called speculative execution, a feature that allows for faster execution of code. Meltdown exploits the fact that low-privilege code and high-privilege memory are not separated properly …

Codasip to Present at Events in Japan and California

October 11, 2017 Blog, News & Docs

Busy October brings many events all over the globe where Codasip will be represented. Apart from Mentor Forums for Emulation in India, Codasip’s VPs and directors will be presenting at the following events. Design Solution Forum Yokohama, Japan | 13 October, 2017 On Friday October 13th, Design Solution Forum will take place in Yokohama, Japan. Codasip’s Director for EMEA Business …

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