We will keep you posted about our endeavors to make ASICs more accessible.
Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power & area) numbers. In theory, they should provide a level playing field for comparing different processor IP cores, but in reality, the situation is more complex. Let us consider performance.
Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power & area) numbers. In theory, they should provide a level playing field for comparing different processor IP cores, but in reality, the situation is more complex. Let us consider performance.
In the last three months, Codasip’s RISC-V processor offering has expanded considerably. For some years, Codasip has supplied Bk3 and Bk5 RISC-V cores aimed at low- to medium-complexity embedded applications. But recently four additional cores have joined the Codasip RISC-V offering.
The Moore’s law has had remarkably long validity of almost half a century. Today, however, it is ceasing to apply, opening new pressing questions such as: How to make up for the fact that chip size cannot be effectively reduced any more? What is the new way to improve performance? Roddy’s blogpost digs into one of the most promising answers: Core customization. Read on!
The Moore’s law has had remarkably long validity of almost half a century. Today, however, it is ceasing to apply, opening new pressing questions such as: How to make up for the fact that chip size cannot be effectively reduced any more? What is the new way to improve performance? Roddy’s blogpost digs into one of the most promising answers: Core customization. Read on!
Using open-source is appealing, but also challenging. Can there be solid support for open core deployment? What will be the “Linux way” in the hardware domain?
It is often implied that if you use an open source processor core there are no costs associated with using it. Is that actually true?
Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, has selected Questa® SLEC by Mentor for use as part of its comprehensive verification flow. The Codasip verification team expects this will significantly reduce the time needed to ensure logical equivalence of multiple HDL representations of each of its processors.
Embedded World 2018, the international trade fair for embedded systems, took place between February 27th and March 1st in Nuremberg, Germany. This year, the event enjoyed a record number of participants and a strong presence of RISC-V. In 2016, a visitor to Embedded World saw a set of offerings almost identical to the previous decade – the same semiconductor vendors, software development tool companies, system level offerings. The dominant …
Brno, Czech Republic – February 21st 2017 – In the past weeks, Codasip has been not only planning and expanding business, but also hiring and growing in the personnel area. The main focus stays on the headquarters office in Brno where the whole development team is based. With yearly supplies of young talents fresh from universities, an ideal location in …
