Configurable LLDB for (not only) embedded RISC-V processors

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At some point, software developers or processor developers need to check and debug their code. They can do this at different levels, for example looking at waves or parsing printouts, but the preference is to check code in an interactive session. The debugger facilitates the interactive session by accepting developers’ commands, executing them, and showing […]

How the SYCLOPS project democratizes AI acceleration

Codasip Labs is all about innovation, and specifically the commercialization of that innovation. Naturally, with the rise of Artificial Intelligence (AI) and Machine Learning (ML), these areas have become a key focus for us. At the beginning of 2023, we joined the New Horizon Europe Project SYCLOPS (Scaling extreme analYtics with Cross-architecture acceLeration based on […]

Re-targetable LLVM C/C++ compiler for RISC-V

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RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and differentiation without fragmentation. On top of the baseline modules from ratified/standard ISA extensions, such as integer instructions or floating-point instructions, designers can add custom instructions: pure design freedom! And the reasons for adding instructions are many: better performance, smaller […]

Making the most of the 60th DAC

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I just returned from a week in San Francisco where I attended the 60th Design Automation Conference. It was a typical week at DAC — cold weather in July, catching up with long-time industry friends, and lack of sleep from long days. Maybe I’m just cynical from having been to DAC since 1995 — which […]

Codasip Studio 9.2.0: what’s new?

Codasip Studio in its 9.2.0 release is now available. This new version of our unique processor design automation toolset comes with a series of new features that both expand and optimize its applications. The new features supported in Codasip Studio 9.2.0 include: Macro Processor. Arrays in CodAL. uRISC-V 2.0. Pipeline definition in modules. Simulator Save state and […]