Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

Embedded World 2022 – the RISC-V genie is out of the bottle


June 28, 2022

The last Embedded World was back in February of 2020, but the event was hit hard by Covid-19 with many exhibitors and visitors deciding to pull out last minute. No-one knew then that it would take almost two and half years before the embedded industry would regroup again in Nuremberg. Even now, in June 2022, a lot of people are still hesitant to travel and the volume of visitors in the halls was half this time compared to the glory days of 2018 or 2019. However, compared to December 2021 and the RISC-V Summit in California, this time there were no empty aisles and there was a steady flow of visitors walking the halls. Embedded World 2022 was an important conference for us and the RISC-V community.

Everyone knows about RISC-V and Codasip is no longer a well-kept secret

You know when you meet children that you have not seen in a few years and cannot get over how much they have grown? Well, probably some people had that same experience with RISC-V this time around at Embedded World 2022. Because it was evident that RISC-V is all grown up now!

Thinking back to my second week at Codasip in 2017, I was at our stand at Embedded World. We had displays that spoke of RISC-V and processor design automation, but our exhibit caused raised eyebrows. The typical passer-by simply said, “What is RISC-V?” or “who are you?”.

In contrast, by this year, everyone knows about RISC-V, students and large and small corporations alike. We were also a strong contributor of presentations to the RISC-V Pavilion too. And a good thing for us here at Codasip is that most people seem to also know us as a leading RISC-V IP provider.

Our-team-gave-three-talks-at-the-RISC-V-pavilion-during-the-conference
Our-team-gave-three-talks-at-the-RISC-V-pavilion-during-the-conference

Codasip is also no longer a well-kept secret, and we were well sought out by customers, partners and the media. Whether it’s our technology, or because of all the recruitment activities, it’s evident we’ve created a lot of interest. (And yes, we are still hiring, check out our open positions.)

If someone wasn’t sure what Codasip does, they most probably do after this week. Our customizable, low-power L31 embedded processor was awarded an Embedded World Best in Show by Embedded Computing Design magazine and the strong team on the Codasip stand was demonstrating our capabilities in delivering low-power embedded AI. In addition, we announced Apple macOS support in Codasip Studio, plus secure boot for Codasip processors, in collaboration with Veridify, and our friends at XtremeEDA and Crypto Quantique announced secure deployment using Codasip IP.

Brett Cline receiving the Best-In-Show award in the name of Codasip for our L31 processor IP
Brett Cline receiving the Best-In-Show award in the name of Codasip for our L31 processor IP

What was the buzz from the show floor?

Well, one company in security software whose offering is partly based on standards driven by Arm said they were expanding into RISC-V, because their customers wanted easier migration from Arm to RISC-V. In contrast though, another security software company said that for them they were not yet ready to support RISC-V based on the limited number production RISC-V devices in the field. But given the interest in RISC-V that would change in time. The industry is definitely at a tipping point – the RISC-V genie is out of the bottle!

Also, we heard an opinion about RISC-V compiler quality being better than Arm, which is interesting indeed.  There’s a long way to go, but with a rapidly growing ecosystem delivering a plethora of customizations and optimizations using the open RISC-V ISA, and with better tools on top of that, RISC-V is outstripping expectations and increasingly we think RISC-V is really starting to keep Arm and other established ISAs awake at night.

The next chance to meet the Codasip team is at DAC, at the Moscone Center in San Francisco on July 10-14 in booth #1451.

Meet us at DAC

Roddy Urquhart

Roddy Urquhart

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Building the highway to automotive innovation


May 5, 2022

The semiconductor industry has changed and nowhere is this more visible than in the automotive industry. Global chip shortages have highlighted how dependent we are on silicon to keep cars on the roads. These shortages are also keeping wait times for new vehicles at an all-time high.

Add to this an influx of non-traditional players into the market and it’s easy to see why the automotive sector is arguably the hottest in the tech world right now. A new marketplace in automotive innovation and technology is taking shape with a battleground between existing pillars, tech giants and new business models. The ability to differentiate in this market is the key to success, bringing subtly different needs and requiring solutions with a different approach.

The electronics needs of the car are changing but always come back to compute

Two things are fundamentally changing in the automotive industry: the concept of software-defined vehicles (SDVs) and the need for democratizing innovation at design level. This transition from hardware to software unlocks new services and solutions for car manufacturers, enabling the delivery of updates and upgrades over the air for a better driver experience. And here, computing is a focus for the next generations of vehicles.

Bringing hardware closer to the system engineering is a different approach and exactly what Codasip can enable. The combination of Codasip Studio technology with RISC-V processor IP delivers access to rapid innovation, ownership and cost reduction right into the hands of automotive players. These are companies of all sizes that are experiencing the pains today. Democratizing processor design is a real demand that is accelerating automotive innovation in the supply chain. Codasip and RISC-V offer the ability to innovate rapidly at design level by reducing cost and complexity.

The need for ownership in the automotive sector

The ability to differentiate in a rapidly evolving sector such as automotive is key to success, or even survival. Owning the ability to Design for Differentiation is crucial and that is exactly what Codasip enables.

Centered in Europe, we are surrounded by the world’s largest market for automotive innovation and manufacturing and away from geopolitical challenges. We are surrounded by leading experts and customers and are able to work closely with them to build a world-class capability by deeply understanding the challenges and find solutions. These solutions benefit our automotive customers and their end customers – as well as the wider automotive industry, to some extent.

Design for differentiation is our buzzword. We are unlocking the true potential of RISC-V by providing our customers with best-in-class quality IP and processor design automation technology with the potential to enable and accelerate the innovation that the automotive industry needs through processor customization. In a reshaping world and supply chain, we are enabling innovation at a much lower cost, removing the barrier to entry, leading into ownership of the processor design.

Security and safety embedded by design

Having security and safety embedded by design and allowing our customers to rapidly make changes to the design while maintaining safety, security integrity and proof of the design – without a lengthy design cycle – is fundamental.

Despite chip shortages, chip innovation is booming and that applies especially to the automotive sector. It is abundantly clear that the future of automotive is through innovation and differentiation. Codasip’s processor design automation technology and EDA tooling has the potential to accelerate innovation in the automotive supply chain, and to enable innovation in electrification and safe and secure applications for connected and autonomous vehicles.

Jamie Broome recently joined Codasip as VP Automotive after more than 20 years at Imagination Technologies. Read the press release on his appointment and the exciting opportunities ahead for Codasip and the industry.

Jamie Broome photo 2

Jamie Broome

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A European Opportunity for Codasip


March 10, 2022

Why did I join Codasip a couple of days ago as VP of Sales for EMEA? We could sit down here and discuss for a few hours, but perhaps I should keep it short for now. Number 1: The RISC-V revolution is happening and Codasip is one of the leaders in the industry. Number 2: The market opportunity is ripe. It is time we make sure the European semiconductor industry understands the value and Design for Differentiation offering from Codasip.

The RISC-V revolution is happening

Did you know that Codasip was founded in 2014 with the launch of Codasip Studio™, and that a year later it co-founded RISC-V International with other key players in the industry? And that same year, in 2015, Codasip launched its first RISC-V processor core? Codasip was definitely a pioneer of that revolution and is today a true leader with strong foundations to build on.

The semiconductor industry today thrives on innovation choice and diversity. Scaling is failing and the only way in the short-term is to take specialization further by creating innovative architectures and domain-specific accelerators for tackling specialized processing problems. Instead of the classic approach of tailoring software to available microprocessors it is now necessary to create hardware that is designed to match a software workload. This can be achieved through customizing an ISA, creating special microarchitectures, or creating novel processing cores and arrays. That’s exactly what RISC-V is perfect for.

With a portfolio of best-in-class quality processors and unique design automation technology, Codasip opens a new avenue for the industry. We enable processor customization in matter of months, allowing our customers to create the compute engine that is right for their algorithm. Across many use cases, this results in unparalleled advantages without compromising time to market.

Advanced processes cannot be the only answer to higher performance. Rethinking how processors can be altered so that they may be exploited to their full capacity for different uses cases is a disruptive and very elegant approach to overcoming performance, power, and cost bottlenecks. Codasip is the undisputed leader in this field. As our CMO Rupert Baines said, now is the right time to join Codasip and be part of the RISC-V revolution.

Right here, in Europe

Codasip is strongly anchored in Europe, and so am I. Codasip is definitively a global company but a strongly and strategically European in a way that sets it apart from its competitors.

Given the strategic importance of Europe in the global chip economy today, Codasip is in the right place at the right time to help bolster the region’s industry, and it is fundamental that our customers in Europe know that. On one hand, Europe is building its own initiatives to boost the semiconductor industry and to enhance its self-sufficiency. The European Chips Act is set to drive initiatives, Intel sees a strategic neutrality of Europe and is investing $20Bn in fabs in Germany plus Tower Fabs in Israel.

At a time when there is at least a short to mid-term shortage in the supply of chips, Europe’s initiatives are likely to strike a chord with the needs of the industry. Added to that, Codasip is strategically located in Europe making us well-positioned to work with Chinese or US companies.

With a strong portfolio of RISC-V processor IP and unique Studio custom design tools, companies of all sizes are able to quickly, easily and cost-effectively benefit from Codasip’s Design for Differentiation offering. There is work to be done in educating the EMEA market, but it is clear that Codasip delivers significant value.

Being French and British and having operated in this region most of my career, I cannot wait to work with key European customers in addition to the leading customers Codasip has all around the world, to enter long-term strategic partnerships as RISC-V is becoming the inevitable architecture computing is gravitating towards.

Emmanuel Till Vatier from Codasip

Emmanuel Till-Vattier

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How to extend the ‘unscalable’ RISC architectures


February 18, 2022

A couple of years ago, Erik McClure (a Microsoft software developer, at the time) published a blog entitled, RISC Is Fundamentally Unscalable.

This blog was really quite interesting and made some very good points about the limitations of a pure RISC design.

The limitations of a pure RISC design

It takes me back: some of my first marketing tasks were around the religious war between RISC & CISC.

However, to a degree, I think Erik’s blog overstates things: nobody today really thinks of RISC-V as being just RISC.

That religious war is long-gone: we have all read Hennessy & Patterson, we all know to use quantitative technique and metrics to analyze performance and to make the inevitable trade-offs. Complex instructions, deeper pipelines, faster/cleaner architectures, power versus area versus performance – those are solved by modelling & data not simplistic binary divides or theological purity.

A key principle of RISC-V from its inception was the ability to add instructions, and there are a number of defined extensions, as optional modules.
There certainly are products using standard RISC-V cores with the standard base ISA. But there are many products with extensions. And for many applications you can do even better. 

Extending RISC architectures with customization

This ties in very well with the Codasip philosophy: the use of RISC-V as a basic architecture for the benefits of interoperability ecosystem partners and ready-made software. But then add custom instructions for exactly the situation that you need.

For some applications that might be the astonishing “Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero” that he describes in the blog. But for other applications it will be a suite of instructions tailored to AI or ML operations because that is what the system needs. Or it might be instructions for video processing or audio processing because that is what instructions this system needs.

Image source: Codasip.

Chips are designed for a purpose – processors are used for an application. In some cases, yes, that is a general-purpose processor, and it must cope with all manner of weirdness and generic, unpredictable code. In which case yes, it’s entirely possible the instruction set will grow and grow as we can see in X86 or Arm. This is one reason the RISC-V International organization is proposing profiles with the most common configurations and extensions.

However, in many applications the system is used for a particular purpose running a particular codebase.  In that case there’s absolutely no need for the instruction set to become huge: it can be RISC as always intended with a small instruction set, small die area with no overhead and just a few custom instructions for those few very performance-sensitive, critical purposes.

That gives the best of all worlds: high-performance, a small, optimized architecture, industry compatibility, software ecosystem, and yet both area-efficient and power-efficient because there is no need for all the custom logic adding complexity for things that are not required in that application.

There is always a need for basic commonality and interoperability to avoid fragmentation, to get the benefits of the RISC-V ecosystem. But for many systems the best processor is one tailored for its task. RISC-V enables that flexibility and Codasip delivers it.

Rupert Baines

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Scaling to new heights at Codasip


December 2, 2021

Scaling is failing is a drum we’re banging here at Codasip: the end of Moore’s Law, Dennard Scaling, Amdahl’s limits… Semiconductor process shifts are costing more but no longer providing the expected and required performance improvements.

Something must be done, and fortunately there is RISC-V with its open ISA that lets designers tune not only the microarchitecture, but the ISA itself, to co-develop hardware and software and provide truly optimized performance, power, and area. Codasip’s Studio™ EDA tool and CodAL processor description language are arguably the easiest and most proven way to make such customization.

Image source: Codasip.

Customers today are telling us that they want more “heterogeneous compute” and “domain specific acceleration”, a topic covered by our CMO Rupert Baines in a post about Apple’s recent M1 Pro launch.

And this is exactly the Design for Differentiation Codasip is providing for our customers. Our incredibly supportive existing and new investors are committed for the long-term to expand Studio, CodAL, and our portfolio of RISC-V cores to include the high-end and new functionality we will unveil in the coming quarters.

As we keep saying, Codasip has been a well-kept secret, but will not be for much longer. Indeed, our customers have already deployed an estimated 2 billion cores designed with Codasip tools!

Dr Ron Black was appointed as Codasip’s CEO today (2 December 2021), read the news here.

Ron Black, CEO. Source: Codasip.

If you want to hear more about #ScalingIsFailing, come along to my #RISCVSummit keynote on Wednesday, December 8th at 14:10 PST (that’s 2210 GMT/UTC), find out more on our RISC-V Summit 2021 page – hope to see you there, in person or virtually.

Ron Black

Ron Black

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Why it’s the perfect time to join Codasip and be part of the RISC-V revolution


September 13, 2021

Eighteen months ago, I said: “The rise of RISC-V offers us a tremendous platform for innovation and collaboration: it has the potential to change the business model of the entire industry.” I stand by that and indeed am demonstrating my conviction by joining the ranks of a company that’s not only changing the industry business model, but is significantly innovating in RISC-V.

Having taken UltraSoC to its exit (sold to Siemens in June 2020), I was on the lookout for the next opportunity. It didn’t take research to know I wanted to be part of RISC-V. And Codasip has an incredibly strong team I know and respect – having worked with them, via our partnership at UltraSoC, or having known through previous roles in the industry. I jumped at the opportunity to work with a European company in such a strong market position.

Codasip is like other RISC-V IP vendors in that we have a portfolio of standard cores for those who want a standard product. But we have something unique: the custom capabilities of Codasip Studio that take the open-market opportunities of RISC-V to a new level. This radically simplifies the task of differentiation and offering our customers the ability to embed unique features. This creates a virtual bridge for those companies who want the ecosystem of a standard ISA, but also want the flexibility of a custom-designed processor.

The industry momentum and interest in RISC-V continues to grow, unabated… in fact, with even more impetus. Why is this? Well, as I’ve long since preached (I’m told I preach!) since its inception, RISC-V has represented a fundamental shift in the industry – a shift in processor architecture that is only just starting.

Arm has transformed the industry and still (rightly) has a significant following for its architecture. But no-one can deny there are questions over where the company is heading and concern over the implications and longer-term design choices. That is opening up the market to the benefit of SoC designers and the industry as a whole – and, of course, to the benefit of alternative solutions like Codasip.

This is a timely opportunity for RISC-V. And Codasip, with its Studio platform, finds itself at the sweet spot: offering customers all the benefits of the open-standard RISC-V ecosystem combined with the ability to customize and differentiate their designs. This is the best of both worlds – offering a unique value to a significant portion of the market.

Codasip’s proposition means it already has excellent customer traction – it was one of the first companies to commercialize RISC-V IP – but the fact it remains (mostly) a well-kept secret is, from my point of view, a marketing dream come true and a challenge I relish!

Rupert Baines

Rupert Baines

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A Tale of Two Approaches to High-Performance IoT


June 21, 2017

EXTENSIBLE PROCESSORS VS ACCELERATORS – AND HOW RISC-V CHANGES THE DYNAMIC

If you were to ask any good designer today what is the best architecture for an SoC that needs to manage complex DSP or high bandwidth traffic demands – you will almost always find the recommendation of using one or more off-the-shelf processors, complimented by hardware accelerators to offload complex processing from the main cores. This solution should give the best power and performance outcome.

The accelerators are usually implemented as standalone RTL blocks connected to the main processor bus, and are optimized to be very efficient on the data types they work with. So on the surface they appear to be the logical choice to deliver optimal power and performance.

BUT, HOW DID THIS COMMON ARCHITECTURE COME ABOUT, AND IS IT ALWAYS THE BEST APPROACH?

The how it came about is an easy answer – it came about because when you have a fixed processor IP and an ISA that you cannot change, the use of accelerator IP to offload complex data manipulations is the only practical solution. So in a world dominated by ARM and MIPS, the use of hardware accelerators was the only option.

As they say, when all you have is a hammer, everything looks like a nail.

So the next part of the question is “Are accelerators the best solution?”

That is a much more nuanced discussion, and it is highly dependent on the specific application. What we can say is that for many of the cases when accelerators are used, they are sub optimal. In the narrow context of their own operation they save power (and processing time), however at a system level it may lead to greater power and processing time than the alternative.

The reason for this is that if you need flexible pre and/or post processing of data in addition to the primary data manipulation of the accelerator – you will find the application performing many CPU operations and many memory operation, in addition to the operation of the accelerator. The net result is that any advantage of the accelerator is offset by the overhead of pre and post processing.

WHAT DOES THIS HAVE TO DO WITH RISC-V?

Since RISC-V is both an Open and Extensible ISA – it means you can build an implementation that is compliant to the standard and as such able to take advantage of the rich software ecosystem (OS’, Libraries, etc) – while at the same time utilizing application specific processor optimization and extensions. Something that is not possible with a traditional ARM or MIPS processor.

The advantages of extensions rather than accelerators is that the main processor can do the needed data transformations in an highly efficient manner.

This means what would be in an accelerator context the following sequence

  • Processor Data read
  • Processor Data Pre Process
  • Processor Data write
  • Accelerator Init
  • Accelerator Data Read
  • Accelerator Data transform
  • Accelerator Data Write
  • Processor Data Read
  • Processor Data Post Process
  • Processor Data Write

Becomes

  • Processor Data read
  • Processor Data Pre Process
  • Processor Data Transform (via processor extensions)
  • Processor Data Post Process
  • Processor Data Write

The drastic reduction in system traffic reduces overall system complexity and power. This is not a new concept, but the advent of the extensible RISC-V architecture makes it easier than ever to achieve.

SO ARE EXTENSIONS ALWAYS THE ANSWER?

I would love to say yes, but that would put us back into the “everything’s a nail” situation. The reality is that it depends on your data and your application.
Thanks to the extensibility of the Codix-Bk Core (RISC-V compliant)  and the ease of modifying the implementation of RISC-V using Codix Optimizer you can easily decide if the best answer is an accelerator, or processor optimization/extensions. This is not something that has been possible previously. Sure there were extensible processors, but they locked you into a closed and limited ecosystem.

With Codasip and RISC-V you get the best of both worlds.

Karel Masarik

Karel Masařík

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