Embedded World 2023: it’s time to architect all ambitions with custom compute
As soon as we arrived in Nuremberg, we could feel the city was buzzing and ready for a great Embedded World 2023 conference. It was hard to avoid exhibitors, speakers, and visitors at breakfast in the hotel or at dinner in restaurants – not to mention the waves in the metro! It was my first […]
Highlights from 2022, a turning year for Codasip
The start of a new year is a perfect time to look back and reflect on the previous year and our company’s position. At the RISC-V Summit at the end of 2021, our CEO Ron Black said that Scaling is Failing, with regard to Moore’s Law, Dennard Scaling, and Amdahl’s Law, and the industry needs […]
Embedded World 2022 – the RISC-V genie is out of the bottle
The last Embedded World was back in February of 2020, but the event was hit hard by Covid-19 with many exhibitors and visitors deciding to pull out last minute. No-one knew then that it would take almost two and half years before the embedded industry would regroup again in Nuremberg. Even now, in June 2022, […]
Building the highway to automotive innovation
The semiconductor industry has changed and nowhere is this more visible than in the automotive industry. Global chip shortages have highlighted how dependent we are on silicon to keep cars on the roads. These shortages are also keeping wait times for new vehicles at an all-time high. Add to this an influx of non-traditional players […]
A European Opportunity for Codasip
Why did I join Codasip a couple of days ago as VP of Sales for EMEA? We could sit down here and discuss for a few hours, but perhaps I should keep it short for now. Number 1: The RISC-V revolution is happening and Codasip is one of the leaders in the industry. Number 2: […]
How to extend the ‘unscalable’ RISC architectures
Semiconductor scaling is failing to meet designers’ needs, customers want more heterogeneous compute” and “domain specific acceleration”
Scaling to new heights at Codasip
Semiconductor scaling is failing to meet designers’ needs, customers want more heterogeneous compute” and “domain specific acceleration”
Why it’s the perfect time to join Codasip and be part of the RISC-V revolution
Customization arises from optimizing a processor IP core to handle a certain workload. In some case it makes sense to design a dedicated core from scratch, but in many cases an existing core may partially meet your requirements and can be a good starting point for your optimized core.
A Tale of Two Approaches to High-Performance IoT
EXTENSIBLE PROCESSORS VS ACCELERATORS – AND HOW RISC-V CHANGES THE DYNAMIC If you were to ask any good designer today what is the best architecture for an SoC that needs to manage complex DSP or high bandwidth traffic demands – you will almost always find the recommendation of using one or more off-the-shelf processors, complimented […]