Codasip Studio and Codasip CodeSpace 8.2 available

News & Docs, Press Releases

Codasip is pleased to announce the availability of Codasip Studio and Codasip CodeSpace 8.2.0. Key features of this release: Support of Compiler Security Features Support of C++ Applications (LLVM 8.0.0) Support of RISC-V External Debug Interface Full changelog is available at: https://support.codasip.com/​downloads/​changelog/ The release is available in the Downloads section of our website: https://support.codasip.com/​downloads/​software/ Any feedback on this release is …

Better Benchmarks through Compiler Optimizations: Codasip Jump Threading

News & Docs, Whitepapers

Jump threading is a type of compilation optimization that aims to produce faster code. Codasip introduced its own implementation of jump threading in its LLVM-based compiler that is a part of Codasip’s unique tool suite, Codasip Studio. Our latest whitepaper describes how the implementation works and how it can be used to improve speed of a program execution, earning better benchmarks along the way.

Codasip Studio and Codasip CodeSpace 8.1 available

News & Docs, Press Releases

Codasip is pleased to announce the availability of Codasip Studio and Codasip CodeSpace 8.1.0. Key features of this release: Added support for SW breakpoints Added support for Synopsys VCS Full changelog is available at: https://support.codasip.com/​downloads/​changelog/ The release is available in the Downloads section of our website: https://support.codasip.com/​downloads/​software/ Any feedback on this release is welcome. Share it with us on [email protected]

Questa SLEC Tool From Mentor, a Siemens Business, to Help Codasip Speed Up Verification of Multiple HDL Outputs

Blog, News & Docs

Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, has selected Questa® SLEC by Mentor for use as part of its comprehensive verification flow. The Codasip verification team expects this will significantly reduce the time needed to ensure logical equivalence of multiple HDL representations of each of its processors.

Codasip Presence at Upcoming Events: China Roadshow, DAC 2019, and RISC-V Workshop Zurich

News & Docs, Press Releases

Munich, Germany – May 6th, 2019 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, is going to be featured at three major industry events around the globe in the second quarter of 2019: China Roadshow 2019, Design Automation Conference in Las Vegas, and RISC-V Workshop in Zurich.  “Getting Started with RISC-V” Roadshow 2019, May 6–16, is …

Codasip Studio and Codasip CodeSpace 8.0 available

News & Docs, Press Releases

Codasip is pleased to announce the availability of Codasip Studio and Codasip CodeSpace 8.0.0. Key features of this release: Introduction of a new Codasip Bus Protocol (CPB) Integration of LLDB Integration of OpenOCD Full changelog is available at: https://support.codasip.com/​downloads/​changelog/ The release is available in the Downloads section of our website: https://support.codasip.com/​downloads/​software/ Any feedback on this release is welcome. Share it …

Codasip to Demonstrate Technology Leadership and Commitment to Open Standards at Taiwan RISC-V Workshop

News & Docs, Press Releases

Munich, Germany – March 7th 2019 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, will address the topics of RISC-V C compiler optimizations and frameworks for ISA compliance in two presentations at the upcoming RISC-V Workshop in Taiwan. In the first presentation, Codasip CTO Zdeněk Přikryl will demonstrate how Codasip generates and optimizes the latest LLVM version …