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Codasip and Metrics Design Automation jointly announce the integration of the Metrics SystemVerilog RTL Simulation Platform within Codasip’s Pro SweRV Core™ Support Package.
In the last three months, Codasip’s RISC-V processor offering has expanded considerably. For some years, Codasip has supplied Bk3 and Bk5 RISC-V cores aimed at low- to medium-complexity embedded applications. But recently four additional cores have joined the Codasip RISC-V offering.
Codasip announces the official release of Bk7, the most advanced core in the Codasip family of RISC-V processor IP to date, built specifically with customization and domain-specific optimization in mind.
Codasip announces that VITEC, the worldwide leader in end-to-end IP video streaming, has selected Codasip’s Bk5 RISC-V-based core for their cutting-edge digital video solutions.
The Moore’s law has had remarkably long validity of almost half a century. Today, however, it is ceasing to apply, opening new pressing questions such as: How to make up for the fact that chip size cannot be effectively reduced any more? What is the new way to improve performance? Roddy’s blogpost digs into one of the most promising answers: Core customization. Read on!
Codasip announces the availability of support to the two new SweRV cores, EH1 and EH2. Both are now available, along with all necessary tools and workflows, within Codasip’s exclusive SweRV Support Package.
The Moore’s law has had remarkably long validity of almost half a century. Today, however, it is ceasing to apply, opening new pressing questions such as: How to make up for the fact that chip size cannot be effectively reduced any more? What is the new way to improve performance? Roddy’s blogpost digs into one of the most promising answers: Core customization. Read on!
Codasip announces the official release of its exclusive SweRV Support Package – a comprehensive service for users of SweRV, the new RISC-V superscalar core developed by Western Digital and available free of charge within the CHIPS Alliance repository.
Using open-source is appealing, but also challenging. Can there be solid support for open core deployment? What will be the “Linux way” in the hardware domain?
It is often implied that if you use an open source processor core there are no costs associated with using it. Is that actually true?
