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Codasip announces that NeuLinker, a high-profile Beijing-based company focused on cutting-edge custom computing technologies, has selected Codasip’s Bk5 RISC-V-based core and the Codasip Studio customization toolset for their AI and security-powering solutions.
Codasip announces opening a new strategic design center in France, which is going to play an important role in the company’s innovation and development plans.
For each embedded product, software developers need to consider whether they need an operating system; and if so, what type of an OS. Operating systems vary considerably and the choice of one for your processor core has important implications. Let us explore them.
Codasip is pleased to announce the availability of Codasip Studio and Codasip CodeSpace 8.4.0. Key features of this release: WFI Automation Interconnect Parametrized RTL Full changelog is available at: https://support.codasip.com/downloads/changelog/ The release is available in the Downloads section of our website: https://support.codasip.com/downloads/software/ Any feedback on this release is welcome. Share it with us on [email protected]
The RISC-V ISA is designed in a modular way, meaning that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows implementing precisely the instruction groups that the domain needs, without having to pay for area or power that will not be used.
Mythic, the provider of a unique AI compute platform, was designing an innovative intelligence processing unit (IPU) and found themselves in need of a very specific core that was not available on the market. Mythic created it in Codasip Studio, starting from the off-the-shelf Codasip Bk3 core, and got their optimized domain-specific core without compromises or delays.
Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power & area) numbers. In theory, they should provide a level playing field for comparing different processor IP cores, but in reality, the situation is more complex. Let us consider performance.
Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power & area) numbers. In theory, they should provide a level playing field for comparing different processor IP cores, but in reality, the situation is more complex. Let us consider performance.
Codasip and Metrics Design Automation jointly announce the integration of the Metrics SystemVerilog RTL Simulation Platform within Codasip’s Pro SweRV Core™ Support Package.
In the last three months, Codasip’s RISC-V processor offering has expanded considerably. For some years, Codasip has supplied Bk3 and Bk5 RISC-V cores aimed at low- to medium-complexity embedded applications. But recently four additional cores have joined the Codasip RISC-V offering.
