Codasip to Present at Events in Japan and California

Blog, News & Docs

Busy October brings many events all over the globe where Codasip will be represented. Apart from Mentor Forums for Emulation in India, Codasip’s VPs and directors will be presenting at the following events. Design Solution Forum Yokohama, Japan | 13 October, 2017 On Friday October 13th, Design Solution Forum will take place in Yokohama, Japan. Codasip’s Director for EMEA Business …

Codasip to present at Mentor Forums for Emulation in India

Blog, News & Docs

Hyderabad, India | 10 October, 2017 Bangalore, India | 12 October, 2017 As the verification and validation requirements for modern systems become more and more complex, hardware emulation with its versatility becomes the methodology to go to. At Mentor Forums for Emulation 2017, this shift in emulation usage will be explained and discussed through a number of talks by highly …

Codasip Announces Latest RISC-V Processor

News & Docs, Press Releases

The Newest Codasip RISC-V Processor is Ideal for IoT Designs Brno, Czech Republic – August 21st 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced the newest addition to their Berkelium (Bk) family of RISC-V processors. The Codasip Bk-1 processor is an FSM processor targeted at the Internet of Things (IoT) by offering ultra-low power, the …

Codasip and UltraSoC collaborate on RISC-V trace support

News & Docs

UltraSoC today announced its work on adding trace functionality to the RISC-V specification, and Codasip along with 4 other IP vendors have pledged support. Read more in the announcement at

Visit Codasip @ChipEx2017

News & Docs

We are once again excited to be part of ChipEx2017, the largest annual event of the Israeli microelectronics industry. The event takes place May 9-10, 2017 in Tel Aviv. Drop by our booth to learn about the exciting development in our Codix Cores – especially our newest RISC-V offerings, as well the latest that Codasip studio has to offer. If …

Codasip at the RISC-V workshop, Shanghai, China

News & Docs

As an founding member of the RISC-V foundation, we are excited to be once again part of the latest RISC-V workshop being held May 8-11 in Shanghai China. On the Monday tutorial session we will be presenting an overview of our technology, and at 3:00PM on Tuesday our verification lead Marcela Zachariasova will co-present with Mentor Graphics our approach to streamlining …

Codasip Studio and Codasip CodeSpace 6.6 available

News & Docs

Codasip CodeSpace and Codasip Studio are available for download in the latest version 6.6. The tools contain new features including: Build of simulator and profiler is optional for ASIP New SystemC co-simulator for MS Visual Studio 2013/2015 Support for random memory latency For a full list of features please login to the support area and check the changelog.

Codasip Studio and Codasip CodeSpace 6.5 available

News & Docs

We are proud to announce that the Codasip Studio and Codasip CodeSpace in version 6.5 are available for download. This release includes many improvements and new features including: LLVM 3.9.1 with a new smart code size reduction feature Enhanced debugging including a new scripting support Enhanced profiling including CodAL Expression Coverage More flexibility in a definition of reset modes in RTL …

Visit Codasip @Verification Futures 2017

News & Docs

Visit Codasip at Verification Futures 2017 We are happy to announce that Codasip will be part of the Verification Futures 2017 conference and exhibition, which takes place in Reading on 6th April 2017. Our speaker Andrew Betts will present the challenges and strategies for RISC-V functional verification. Verification Futures 2017