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Codasip CodeSpace and Codasip Studio are available for download in the latest version 7.0. The tools contain new features including: Update to Codasip MINGW 2, which includes MSYS2 and gcc 6.4.0 New interface methods in CodAL Integration of LLVM 5.0.0 Experimental support for AMBA busses For a full list of features please login to the support area and check the …
Learn how to incorporate Questa® VIP into your existing RISC-V verification flow. The tutorial, prepared by Codasip’s verification experts, explains the concepts of combining automatically generated UVM with QVIP and guides you through the process.
Brno, Czech Republic – November 28th, 2017 – Codasip, the leading supplier of RISC-V® embedded processor IP, today announced that it has expanded its Berkelium processor portfolio to include the Bk5-64, its first implementation of the 64-bit RISC-V ISA. Codasip now offers customers the broadest selection of RISC-V processors in the market, spanning from the ultra-low-power zero-stage Bk1 to the high-data-bandwidth, …
Codasip CodeSpace and Codasip Studio are available for download in the latest version 6.10. The tools contain new features including: Support for 2-wire JTAG (IEEE 1149.7) HDK configuration manager JTAG support for syscalls For a full list of features please login to the support area and check the changelog.
Codasip CodeSpace and Codasip Studio are available for download in the latest version 6.9. The tools contain new features including: New HTML based dashboard containing tutorial and example models Integration of LLVM 4.0.1 For a full list of features please login to the support area and check the changelog.
Brno, Czech Republic – October 16th 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced that Chris Jones has joined as Vice President of Marketing, reporting to CEO Karel Masařík. “We are very pleased to add Chris to the Codasip executive team,” declared Karel Masařík, CEO and founder of Codasip. “As we execute our strategy to be the leading supplier of RISC-V based …
Busy October brings many events all over the globe where Codasip will be represented. Apart from Mentor Forums for Emulation in India, Codasip’s VPs and directors will be presenting at the following events. Design Solution Forum Yokohama, Japan | 13 October, 2017 On Friday October 13th, Design Solution Forum will take place in Yokohama, Japan. Codasip’s Director for EMEA Business …
Hyderabad, India | 10 October, 2017 Bangalore, India | 12 October, 2017 As the verification and validation requirements for modern systems become more and more complex, hardware emulation with its versatility becomes the methodology to go to. At Mentor Forums for Emulation 2017, this shift in emulation usage will be explained and discussed through a number of talks by highly …
The Newest Codasip RISC-V Processor is Ideal for IoT Designs Brno, Czech Republic – August 21st 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced the newest addition to their Berkelium (Bk) family of RISC-V processors. The Codasip Bk-1 processor is an FSM processor targeted at the Internet of Things (IoT) by offering ultra-low power, the …
UltraSoC today announced its work on adding trace functionality to the RISC-V specification, and Codasip along with 4 other IP vendors have pledged support. Read more in the announcement at http://www.ultrasoc.com/ultrasoc-announces-industrys-first-processor-trace-support-risc-v/
