Here you can find all News, Press Releases and Whitepapers
Codasip CodeSpace and Codasip Studio are available for download in the latest version 6.6. The tools contain new features including: Build of simulator and profiler is optional for ASIP New SystemC co-simulator for MS Visual Studio 2013/2015 Support for random memory latency For a full list of features please login to the support area and check the changelog.
We are proud to announce that the Codasip Studio and Codasip CodeSpace in version 6.5 are available for download. This release includes many improvements and new features including: LLVM 3.9.1 with a new smart code size reduction feature Enhanced debugging including a new scripting support Enhanced profiling including CodAL Expression Coverage More flexibility in a definition of reset modes in RTL …
Visit Codasip at Embedded World 2017 – Hall 3-627 Codasip will demonstrate the Codix-Bk (RISC-V) development platform running on MicroSemi FPGAs including advanced debug from UltraSoC and quantum resistant security extensions from SecureRF. Embedded World 2017
Visit Codasip at Verification Futures 2017 We are happy to announce that Codasip will be part of the Verification Futures 2017 conference and exhibition, which takes place in Reading on 6th April 2017. Our speaker Andrew Betts will present the challenges and strategies for RISC-V functional verification. Verification Futures 2017
Visit Codasip at REUSE2016. We are happy to be part of REUSE2016 event Dec 1st 2016 with Codasip RISC-V processor IP and Processor development tools. http://www.reuse2016.com/
We are excited to be part of the SemIsrael event Nov 15th 2016. If you are planning on being there drop by and find out more about Codasip IP, RISC-V and Processor development tools. http://expo.semisrael.com/exhibition
We are proud to announce the latest version of Codasip studio is available for download, as well as a new member of the product family Codasip CodeSpace – an IDE (based on Studio) that is designed for ASIP and Codix SW designers. This release include many improvements and new features including; New PPA comparisons to highlight how changes impact the CPU …
We are proud to have the opportunity to be part of the RISC-V (riscv.org) activities at this years Linley Processor Conference. If you are planning on being there drop by the RISC-V demo table during the Tuesday Reception and say Hi. We will be demoing a Quantum Resistant Security implementation by SecureRF built on an extended version of our Codix-Bk …
The major theme for the 6.0 release has been scalability and the ability to create and reuse ASIP projects in a hierarchal manner. In addition there are significant small enhancements and bug fixes across every aspect of the tools. For a full changelog, please see the download section.
Your design is not the same as anyone else’s, so why is your embedded processor? Codasip will be exhibiting at DAC in Austin June 6–8. Drop by booth #1113 to learn more about; Codasip Studio 6.0: See our improved profiling, debug and design tools that turn anyone into a processor designer. Codix IP Cores: Meet the newest members of the …
