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The Newest Codasip RISC-V Processor is Ideal for IoT Designs Brno, Czech Republic – August 21st 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced the newest addition to their Berkelium (Bk) family of RISC-V processors. The Codasip Bk-1 processor is an FSM processor targeted at the Internet of Things (IoT) by offering ultra-low power, the …
UltraSoC today announced its work on adding trace functionality to the RISC-V specification, and Codasip along with 4 other IP vendors have pledged support. Read more in the announcement at http://www.ultrasoc.com/ultrasoc-announces-industrys-first-processor-trace-support-risc-v/
We are once again excited to be part of ChipEx2017, the largest annual event of the Israeli microelectronics industry. The event takes place May 9-10, 2017 in Tel Aviv. Drop by our booth to learn about the exciting development in our Codix Cores – especially our newest RISC-V offerings, as well the latest that Codasip studio has to offer. If …
As an founding member of the RISC-V foundation, we are excited to be once again part of the latest RISC-V workshop being held May 8-11 in Shanghai China. On the Monday tutorial session we will be presenting an overview of our technology, and at 3:00PM on Tuesday our verification lead Marcela Zachariasova will co-present with Mentor Graphics our approach to streamlining …
Codasip CodeSpace and Codasip Studio are available for download in the latest version 6.6. The tools contain new features including: Build of simulator and profiler is optional for ASIP New SystemC co-simulator for MS Visual Studio 2013/2015 Support for random memory latency For a full list of features please login to the support area and check the changelog.
We are proud to announce that the Codasip Studio and Codasip CodeSpace in version 6.5 are available for download. This release includes many improvements and new features including: LLVM 3.9.1 with a new smart code size reduction feature Enhanced debugging including a new scripting support Enhanced profiling including CodAL Expression Coverage More flexibility in a definition of reset modes in RTL …
Visit Codasip at Embedded World 2017 – Hall 3-627 Codasip will demonstrate the Codix-Bk (RISC-V) development platform running on MicroSemi FPGAs including advanced debug from UltraSoC and quantum resistant security extensions from SecureRF. Embedded World 2017
Visit Codasip at Verification Futures 2017 We are happy to announce that Codasip will be part of the Verification Futures 2017 conference and exhibition, which takes place in Reading on 6th April 2017. Our speaker Andrew Betts will present the challenges and strategies for RISC-V functional verification. Verification Futures 2017
Visit Codasip at REUSE2016. We are happy to be part of REUSE2016 event Dec 1st 2016 with Codasip RISC-V processor IP and Processor development tools. http://www.reuse2016.com/
We are excited to be part of the SemIsrael event Nov 15th 2016. If you are planning on being there drop by and find out more about Codasip IP, RISC-V and Processor development tools. http://expo.semisrael.com/exhibition
