Codasip is pleased to announce the availability of Codasip Studio and Codasip CodeSpace 8.2.0. Key features of this release: Support of Compiler Security Features Support of C++ Applications (LLVM 8.0.0) Support of RISC-V External Debug Interface Full changelog is available at: https://support.codasip.com/downloads/changelog/ The release is available in the Downloads section of our website: https://support.codasip.com/downloads/software/ Any feedback on this release is …
Codasip introduces SweRV Support Package, a comprehensive service for users of SweRV, the new RISC-V superscalar core developed by Western Digital and available free of charge within the CHIPS Alliance repository.
CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced that Codasip GmbH and Munich University of Applied Science have joined the CHIPS Alliance.
Codasip is pleased to announce the availability of Codasip Studio and Codasip CodeSpace 8.1.0. Key features of this release: Added support for SW breakpoints Added support for Synopsys VCS Full changelog is available at: https://support.codasip.com/downloads/changelog/ The release is available in the Downloads section of our website: https://support.codasip.com/downloads/software/ Any feedback on this release is welcome. Share it with us on [email protected]
Munich, Germany – May 6th, 2019 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, is going to be featured at three major industry events around the globe in the second quarter of 2019: China Roadshow 2019, Design Automation Conference in Las Vegas, and RISC-V Workshop in Zurich. “Getting Started with RISC-V” Roadshow 2019, May 6–16, is …
Codasip is pleased to announce the availability of Codasip Studio and Codasip CodeSpace 8.0.0. Key features of this release: Introduction of a new Codasip Bus Protocol (CPB) Integration of LLDB Integration of OpenOCD Full changelog is available at: https://support.codasip.com/downloads/changelog/ The release is available in the Downloads section of our website: https://support.codasip.com/downloads/software/ Any feedback on this release is welcome. Share it …
Munich, Germany – March 7th 2019 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, will address the topics of RISC-V C compiler optimizations and frameworks for ISA compliance in two presentations at the upcoming RISC-V Workshop in Taiwan. In the first presentation, Codasip CTO Zdeněk Přikryl will demonstrate how Codasip generates and optimizes the latest LLVM version …
Munich, Germany – December 17th 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, announced today that Vidtoo Technology, a leader in semiconductor products for machine learning and high-performance computing, has selected Codasip’s Bk3 processor for future HPC chips. Vidtoo Technology, based in Hangzhou, China, focuses on high-bandwidth, high-performance, high-connectivity, artificial intelligence platforms and inference engines for data centers as …
Campbell, California – December 10th 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, announced today that Mythic, a leader in artificial intelligence (AI) computing technology, has selected Codasip’s configurable Bk3 processor and Codasip Studio for future neural networking chips. Mythic, based in Redwood City, California, and Austin, Texas, will deliver powerful, life-enhancing AI solutions that customers can push into …
Munich, Germany – December 6th, 2018 – CodasipGmbH, the leading supplier of RISC-V® embedded processor IP, announced today the latest version of Studio, a suite of tools optimized for the development and verification of RISC-V processors, and the Bk7 processor, the first Codasip RISC-V core optimized for Linux and real-time performance. “As the RISC-V ISA specification evolves and adds an ever-increasing number of …
