Press Releases Archives | Page 3 of 6

Codasip Awarded European Union Horizon 2020 Funding for Developing New RISC-V Processors

March 18, 2020

Codasip announces that it has received a Horizon 2020 award from the European Union. The award is aimed at developing processor cores for the rapidly growing market for integrated circuits for Internet of Things (IoT), connected cars, drones, and artificial intelligence.

Codasip teams up with Western Digital to support adoption of open-source processors

December 10, 2019

Codasip introduces SweRV Support Package, a comprehensive service for users of SweRV, the new RISC-V superscalar core developed by Western Digital and available free of charge within the CHIPS Alliance repository.

CHIPS Alliance growth continues with new members and design workshop this November: Codasip and Munich University of Applied Science become members

October 15, 2019

CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced that Codasip GmbH and Munich University of Applied Science have joined the CHIPS Alliance.

Codasip Presence at Upcoming Events: China Roadshow, DAC 2019, and RISC-V Workshop Zurich

May 6, 2019

Codasip Studio and Codasip CodeSpace 8.0 available

March 26, 2019

Codasip is pleased to announce the availability of Codasip Studio and Codasip CodeSpace 8.0.0. Key features of this release: Introduction of a new Codasip Bus Protocol (CPB) Integration of LLDB Integration of OpenOCD Full changelog is available at: https://support.codasip.com/downloads/changelog/ The release is available in the Downloads section of our website: https://support.codasip.com/downloads/software/ Any feedback on this release is welcome. Share it …

Codasip Releases Studio 8, a Breakthrough in RISC-V Automation, and the Bk7 RISC-V Processor Core for Real-Time Computing Applications

December 6, 2018

Codasip Secures $10M in Series A Financing to Expand RISC-V Processor Technology Offerings

December 4, 2018

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Codasip Awarded European Union Horizon 2020 Funding for Developing New RISC-V Processors

Codasip teams up with Western Digital to support adoption of open-source processors

CHIPS Alliance growth continues with new members and design workshop this November: Codasip and Munich University of Applied Science become members

Codasip Presence at Upcoming Events: China Roadshow, DAC 2019, and RISC-V Workshop Zurich

Codasip Studio and Codasip CodeSpace 8.0 available

Codasip to Demonstrate Technology Leadership and Commitment to Open Standards at Taiwan RISC-V Workshop

Vidtoo Technology Licenses Codasip’s Bk3 RISC‑V Processor for High‑Performance Computing SoC

Mythic Chooses Codasip to Deliver RISC-V Computing in their Revolutionary Neural Network Platform

Codasip Releases Studio 8, a Breakthrough in RISC-V Automation, and the Bk7 RISC-V Processor Core for Real-Time Computing Applications

Codasip Secures $10M in Series A Financing to Expand RISC-V Processor Technology Offerings