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Processor design automation to drive innovation and foster differentiation


July 7, 2022

With semiconductor scaling no longer being an option in most situations, optimization means customizing the processor for your specific application. With the right approach and right tools, processor design automation can enable innovation and differentiation. One way of achieving this is to create an application-specific processor by owning the design. To do this efficiently, manual efforts should be reduced to the minimum. Let’s see, in this blog post, how processor design automation can drive innovation and foster differentiation.

RISC-V is bringing design freedom to software and hardware developers

The semiconductor industry is facing scaling limitations (if you haven’t yet, read our white paper on semiconductor scaling) for new applications that require efficient execution of algorithms for data processing. For example, vision, voice and vibration applications. In this context, the only way forward to differentiate is architectural innovation.

The ideal baseline for differentiating is the RISC-V ISA. Free, open, and modular, it allows custom extensions to create a unique processor tailored for specific needs and applications. Most of the time, there is no need to create an entirely new product from scratch. Customizing an existing commercial RISC-V processor is the most efficient way to design a new product with optimal features and PPA.

This approach, which is getting more and more attention, brings new opportunities for software and hardware developers, with complete design freedom. These new opportunities also come with efforts that have not been experienced before. Indeed, any modification to the processor architecture must be reflected in both hardware and software, and be verified. To minimize efforts, make the best use of resources and reduce time to market, processor design automation is key.

Unlocking innovation with processor design automation and Codasip IP and tools

Customization requires the right tools and needs to be considered from the beginning. Codasip RISC-V cores are all designed in CodAL, with customization in mind, so they can be modified seamlessly. Based on C, CodAL is an architecture description language very close to standard programming languages, easy to adopt for processor design automation. This ownership gives you design freedom while keeping control of costs and resources.

Design freedom can start with architecture exploration. Codasip Studio with CodAL generates a Software Development Kit that includes all the tools software programmers will need. Profiling benchmarks, getting performance statistics, making some changes in the design, and seeing the results in just a few minutes: this is all possible with Codasip Studio. But that’s not all.

Codasip Studio workflow
Codasip Studio workflow

Studio and CodAL generate everything needed to be ready for production. Indeed, customization is not just about modifying the RTL. It also includes generating all tools required to design a quality core that can be monetized. Codasip customization solutions take care of this. Customers modify the core as needed in CodAL, the rest is automated.

This unique description language allows the automated generation of the hardware and software tools that are required. With a single, unified toolchain, our customers automatically get the RTL, simulators, testbenches, the verification environment, and a customized compiler that understands their custom hardware and how to take advantage of it. They create a unique product with tools that simplify processor design and verification for all developers.

Processor design automation with Codasip solutions is something we will talk about extensively at DAC 2022 in July, the Design Automation Conference held in San Francisco, California. If you would like to know more about it, visit us at our booth or book a meeting with us.

Visit us at DAC 2022

Lauranne Choquin

Corporate Marketing Manager

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Design for differentiation: architecture licenses in RISC‑V


May 16, 2022

I was discussing with a colleague about the concept of architecture license in RISC-V. I realized that, in the open-source world, it can be a little tricky to grasp.

In a traditional processor IP model, there is a clear distinction between an off-the-shelf IP license that gives some level of configuration but no customization, and a fairly expensive architecture license enabling a licensee to use the instruction set with their own custom microarchitecture.

With RISC-V, the complication comes from the fact that it is often described as “an open-source architecture”, so people believe that some source code is licensed. But actually that is not the case at all.

Traditional IP and architecture licensing

In a traditional model, things are quite straight forward. A standard license for Arm or MIPS lets the customer use an RTL design but not change it at all (aside from a few configuration options perhaps).

Meanwhile, for customers willing to spend a lot of money, an architecture license gives them the right to modify how a processor executes instructions (the issue width, the cache size, etc.). However, it does not generally give the right to modify the instructions (with some exceptions such as the Cortex-M33 that supports Arm Custom Instructions, allowing the implementation of bespoke data processing operations, or Cadence Tensilica).

RISC-V based IP and architecture licensing

In an open-source model such as RISC-V, things are somewhat different

The RISC-V architecture is usually described as “open-source”, which implies everyone can use it at no cost.

However, a better description of RISC-V is that it is an “open architecture” or “open standard”. In that sense RISC-V is like C, Wi-Fi or LTE with RISC-V International performing the role of (respectively) ANSI, IEEE 802.11 and 3GPP in defining and managing standards that people are free to implement as they choose. But that is a written standard – not an implementation or a microarchitecture.

Just as is the case with those other open standards,  RISC-V licenses can either be open-source or commercial.

You can download open-source designs and have complete freedom to modify them however you wish. Boom, PULP, SweRV and other open-source designs give absolute freedom. But that comes with a cost: they are not supported, the verification is often troublesome, and they may not be of sufficient quality to use in a commercial design. Some companies do use them accepting those compromises; others are understandably wary.

Or you can buy a commercial RISC-V design. There are many companies offering high quality cores delivered as RTL with warranty and full product support. These can be an excellent solution for many customers. Then we are back to something similar to the traditional model: a sort of black box design – although based on an open-standard ISA – in that it cannot be modified or customized to address specific needs. But for many purposes that generic product will be a good fit.

Codasip, as a RISC-V core vendor, does a lot of business on this basis: customers buy a standard RISC-V processor core delivered as RTL and SDK, with high performance, “best-in-class” verification and full support. That is without any architecture license fees, to use it as it is, off the shelf.

ISA customization enables Design for Differentiation

But Codasip offers another option. This is an architecture license – and more – delivered as a source code in the CodAL processor description language.

Many of our customers buy a standard Codasip processor IP product delivered as CodAL source and then use Codasip Studio™  which enables them to modify it freely. We provide the flexibility to modify both the microarchitecture and the ISA, precisely what one needs to Design for Differentiation. Customization at ISA level brings higher performance and optimization. What is more, the power and elegance of the Codasip Studio toolset makes this very easy.

This is different to, for example, an Arm architecture license in three ways:

Freedom

Arm, even with an architecture license, constrains what you are allowed to do. Codasip does not: it is your core and you have control.

Tooling

Arm cores are developed internally, in traditional ways and not designed to be easy to modify. In contrast, all of Codasip’s cores are developed using Studio and are designed expressly to make customization (both ISA and microarchitecture) straightforward and efficient. That includes automatically creating the software toolchain (customized compiler etc) and verification.

Cost

Traditionally the limitation of architecture licenses has been both the cash cost of the license and the engineering resources (cost) required to take advantage of it. Codasip and Studio now make that far easier and hence more affordable with a complete end-to-end architecture customization solution. This dramatically changes the cost equation both of the architecture license fee and the engineering resources required.

RISC-V offers the promise of openness: Codasip and Studio make that promise a reality

Codasip offers the best of both worlds: a portfolio of high-quality standard cores that are a good fit for standard applications, with full verification and support. Or you can upgrade to a cost-effective architecture license, freely customize the core in an easy-to-use environment and have a unique product for your unique needs.

Rupert Baines

Rupert Baines

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What is CodAL?


February 26, 2021

CodAL, standing for Codasip Architectural Language, is central to developing a processor core using Codasip Studio. The language has a C-like syntax and it merges good practices and code constructs from conventional programming languages and hardware description languages. It has been developed from the outset to describe all aspects of a processor including both the instruction set architecture (ISA) and microarchitecture.

Each processor description includes four elements in its description:

  1. Architectural resources, for example, registers and a program counter.
  2. Instruction set, that is, names of instructions, their operands and their binary form (opcodes).
  3. Semantics, or a description of the behaviour of each instruction and exception – how they affect the architectural resources.
  4. Implementation, which includes those resources and behaviour (especially timing) that are not visible in the architectural model but which define a particular micro-architectural implementation. Note that more than one micro-architectural implementation can be in a single CodAL description.

The architectural or instruction accurate (IA) model contains the instruction set, architectural resources, and the semantics. The micro-architectural or cycle accurate (CA) model contains the instruction set, architectural resources and the micro-architectural implementation.

CodAL description. Source Codasip.

CodAL description is object-oriented, meaning that an object can be instantiated into a more complex object, the complex object into an even more complex one, etc. CodAL allows information to be passed through the object hierarchy without having to use complex function calls.

The CodAL element is a common example of an object, and in the following example we show an element describing a multiply-accumulate instruction.

CodAL example. Source Codasip.

The use statement describes the resources that are used by the instruction – a destination register (dst) and two source registers (src1, src2). Next, the assembly statement describes the assembler mnemonic (mac) and its arguments. The binary statement describes the binary representation of the instruction and arguments. Finally, the semantics statement describes the multiply-accumulate operation.

The CodAL description is used by the Codasip Studio toolset to generate an SDK and an HDK. For example, the element description would be used when generating the instruction set simulator (ISS), assembler, disassembler, C/C++ compiler, and debugger for the processor core.

CodAL schema. Source Codasip.

The CA description would take advantage of the instruction set and resources descriptions used for the IA models. In addition, the CA description would specify microarchitectural features such as the pipeline length.

The cycle-accurate parts of the CodAL description would be used for generating the cycle-accurate simulator, RTL, testbench, and UVM environment. In this way CodAL is the single source for all aspects of the processor hardware and software. In contrast, some other processor development tools require two languages to describe the processor core. The methodology also enables powerful verification of generated RTL against a golden reference model in generated UVM environment.

Roddy Urquhart

Roddy Urquhart

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