Formal verification best practices: towards end-to-end properties

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In the first two episodes of this blog series, we saw how we put in place an efficient formal testbench for a cache, how we found a genuine bug, reproduced a deadlock bug and found a design fix. At this point we were confident that no other deadlock bug exists. This episode shows how we […]

Formal verification best practices: investigating a deadlock

Formal verification best practices - investigating a deadlock

In our first episode from last week we focused on best practices when setting up formal verification on a component. Our setup is now ready with protocol checkers to avoid unrealistic scenarios (which also helped find a new bug), and with basic abstractions to improve performances. It’s now time to tackle our real task: reproducing […]

Formal verification best practices to reach your targets

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This blog is the first of a series where I will show how to use Formal Verification (FV) with a pragmatic, realistic, predictable,  and efficient approach. The goal of this blog series is not to explain how FV works, but how to use best practices to achieve verification targets. Indeed, having efficient tools is one […]

What you should ask for instead of just PPA

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SoC designers would really like to be able to compare PPA numbers of digital IP. However, as explained in our previous article, this is mostly impossible as available numbers usually do not apply to your use case. It is easy to be misled by PPA. So now, how do you select the best digital IP? […]

Why you should stop asking for PPA

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As a topic that is subject to intense discussions, PPA (Power, Performance & Area) is certainly something that everyone in the semiconductor industry is focusing on. Who wouldn’t want a smaller and cheaper circuit that would consume less power and be much more capable than the previous generation? But you should stop asking for PPA. Or at […]

No one-size-fits-all approach to RISC-V processor optimization

Cover image blog Mike Eftimakis on No one size fits all approach to processor optimization

As the demand for high-performance processors continues to grow and semiconductor scaling laws continue to show their limits, the need for processor optimization is inevitable. As I explained in a previous blog, RISC-V is designed to enable this. However, there is no one-size-fits-all approach to processor optimization. As each workload and each application will have […]

RISC-V customization, HW/SW co-optimization, and custom compute

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Do we still need to introduce and define RISC-V? You know, the open-source instruction set architecture (ISA) that is gaining popularity thanks to its flexibility, scalability, and modularity. Okay, we just did, just to be sure we are all on the same page. One of the key benefits and the main “raison d’être” of RISC-V […]

Creating specialized architectures with design automation

With semiconductor scaling slowing down if not failing, SoC designers are challenged to find ways of meeting the demand for greater computational performance. In their 2018 Turing lecture, Hennessey & Patterson pointed out that new methods are needed to work around failing scaling and predicted ‘A Golden Age for Computer Architecture’. A key approach in addressing this challenge […]