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How to reduce the risk when making the shift to RISC-VIn conversation with Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip


November 17, 2022

With the Intel® Pathfinder for RISC-V* program, Intel launched a development environment that enables companies of all sizes to start their RISC-V journey. Codasip makes its L31 RISC-V embedded core available to the embedded community through the program.

We asked Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip, to tell us more about this.

On the left: Rupert Baines – CMO at Codasip; on the right: Vijay Krishnan – GM, RISC-V Ventures, Incubation and Disruptive Innovation (IDI) Group at Intel Corporation

Vijay, what is the risk when making the shift to RISC-V?

There is real risk and then there is perceived risk. Regarding the former, any architectural transition adds complexity, but with RISC-V the entire hardware and software ecosystem is coming together in a manner which minimizes the real risk, while unleashing the long-term value that comes with an open, modular and modern instruction set architecture. The presence of cores like the Codasip L31 are making it easier and easier for customers to make that transition so they can reap the benefits of RISC-V. Sensors, security IP/software, IoT middleware and cloud connectivity available within the Intel Pathfinder for RISC-V IDE all help to mitigate perceived risk by demonstrating end-to-end capabilities at the pre-silicon stage.

Rupert, do you agree with this, and is RISC-V risky?

Well, the cool thing about RISC-V is that it is an open standard, and that brings so many possibilities. But that can also be a challenge! Endless possibilities make it harder to make a choice and the evolving ecosystem can be hard to navigate.

Intel has blazed a path with Intel Pathfinder for RISC-V by making a first selection of recommended vendors, and from that stamp of quality, companies can explore and evaluate what best fits their needs.

As a key RISC-V processor IP vendor, it was obvious for Codasip to be part of the Intel Pathfinder for RISC-V ecosystem. Our L31 core is quite versatile so we chose to make it available to the wider embedded community through the program. It is a low-power, general-purpose, embedded RISC-V core that balances performance and power consumption. From IoT devices to industrial and automotive control, or as a deeply embedded core in a larger system, it brings local processing capabilities into a compact area.

Who is going to benefit from this Intel & Codasip partnership?

Vijay: The initial beneficiaries are end-user segments addressed by the Codasip L31 core. Over time we hope Intel Pathfinder for RISC-V will include support from a broader range of Codasip cores. By harnessing our combined capabilities, we see a tremendous opportunity to accelerate the transition to RISC-V, thereby establishing it as a third mainstream compute architecture after x86 and Arm.  

Rupert: Companies of all sizes, really. From SMEs to start-ups and bigger players. We give everyone access to high-class silicon ready proof points to get started with their RISC-V journey in a standard and stable environment. If they wonder whether they should go with our L31 core, they can see their use case brought to life. With Intel Pathfinder for RISC-V, our core can be integrated with a growing set of complementary IPs, multiple operating systems, and toolchains for IoT and embedded applications.

Intel Pathfinder for RISC-V and Codasip logos

How is the RISC-V ecosystem doing today?

Vijay: In addition to being open and modular, RISC-V is free and easily licensable. In less than 10 years since its inception, RISC-V has made remarkable progress, driven largely by a well-knit ecosystem that includes academia & research in addition to a breadth of commercial organizations. The opportunities are vast, and based on what we have seen to date, the RISC-V market will reward organizations that not only build competitive products, but also foster collaborative models within the ecosystem.

Rupert: The RISC-V community is growing rapidly and continuously gaining market traction. It is attracting everyone, from university researchers to major industry players. There have been new processors and new ISAs in the past. But what is different about RISC-V is the ecosystem, a critical factor in the success of a processor architecture. More and more players are joining, more and more software and tools are available, broadening the adoption of the ISA. This in turn is attracting more ecosystem partners in an accelerating virtuous spiral, and it is that spiral that is driving the success of RISC-V, in which Intel and Codasip play a major role for the embedded industry.

How is this partnership helping companies make the shift to RISC-V?

Vijay: By combining Codasip RISC-V IP with the Intel Pathfinder for RISC-V developer tools, we are making it easier for customers to go from product concept to a mature platform that includes silicon and software. Intel Pathfinder for RISC-V combines RISC-V IP with complementary security IP, accelerators for AI/ML, Vision and Audio processing, as well as sensor and middleware integration, thus providing an accelerated software development path for customers that reduces time to market, cost and complexity/risk.

Rupert: The program removes the barrier to the adoption of RISC-V by providing a level of standardization that can make RISC-V adoption easy with some level of consistency for the software developer community. By collecting vendors of different types, the program can kickstart the development of a new system by bringing together all the great capabilities already out there, including L31. You can instantly start an IoT application based on our L31 core, combine it with other IP, integrate security from Crypto Quantique, and verify it all using Siemens EDA even before committing to silicon.

Collaboration is key.

Those who collaborate are better set for success in RISC-V than those who don’t. Thanks to an ecosystem coming together, the risk of RISC-V is reduced, and you can easily explore options when you are ready to make the shift. Codasip and Intel are exploring further possibilities for collaboration, and you will see more offerings going forward, always with quality and ease of use in mind.

Give it a try!

* © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. No product or component can be absolutely secure. 

Lauranne Choquin

Corporate Marketing Manager

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5 good things about RISC-V


September 22, 2022

RISC-V has been around for some time now, and if you are here it’s because you have heard of it. But perhaps you still need to be convinced that it is the future? If you still wonder about its potential and benefits, here are 5 good things about RISC-V.

1. RISC-V IS AN OPEN STANDARD

Let’s start simple. This is nothing new, but let’s be clear on what open standard means.

Open standard does not necessarily mean open source. The RISC-V architecture is often described as “open-source”, which is inaccurate. As we explained it in this article on architecture licenses in the context of RISC-V, RISC-V is like C, Wi-Fi, or LTE with RISC-V International performing the role of (respectively) ANSI, IEEE 802.11 and 3GPP in defining and managing standards that people are free to implement as they choose. But that is a written standard – not an implementation or a microarchitecture. Just as is the case with those other open standards, RISC-V licenses can either be open-source or commercial.

Therefore, the RISC-V Instruction Set Architecture (ISA) is open, meaning that it is free and anyone can download the documentation to use it however they like, without asking for anyone’s permission. This is great because it allows smaller developers, companies, and groups such as academics to design and build hardware without paying an expensive proprietary ISA license and royalties. RISC-V is accessible to everyone.

2. RISC-V IS ATTRACTIVE TO UNIVERSITY RESEARCHERS

You may already know that RISC-V started as a university research project in California, at UC Berkeley, back in 2010. As we just mentioned the interesting financial aspect it brings, it is not really surprising to see more and more university researchers looking into it.

Now, researchers can do it two ways. Thanks to the work of various academic institutions such as UC Berkley, there are free open-source implementations of the RISC-V ISA available. These can be used in university projects to do work that would not be possible without an open standard.

To go one step further, universities can also partner with RISC-V companies that are developing university programs. What a great way to prepare today’s students to become the engineers of tomorrow! Codasip for example has a University Program. By cooperating with academia, we can accelerate the development of RISC-V IP and design automation. Having university researchers working on RISC-V is another key to its success in solving tomorrow’s technological challenges.

3. RISC-V ALLOWS FOR CUSTOMIZATION

That’s where the true potential of RISC-V is.

The RISC-V open standard allows people to customize. Most commercial companies do not support this, however. They sell a standard, fixed, product. Of course, if you design your own code, then the freedom is there – but for most people, that is not possible. Some companies, like Codasip, give the best of both worlds: customization and the rich ecosystem of RISC-V. With RISC-V being a layered and extensible ISA, these companies allow you to implement the baseline instruction set, optional extensions, and add custom extensions for a given application.

Let me just clarify one thing here. Don’t mix up customization and configuration. Being able to choose the size of a cache is great, but that’s not customization. Customization means being able to modify the instruction set architecture and the microarchitecture. That’s quite powerful as this is how you design an application-specific processor perfectly tailored to your unique needs.

4. RISC-V GIVES YOU FREEDOM AND OWNERSHIP

Let’s go one step further now. By allowing customization, RISC-V allows you to be independent. You work from an open standard that you can modify as you want. You can now do your own things, your own way, while still talking advantage of the standard RISC-V architecture and software interoperability. That’s something very powerful and that will be crucial in many industry sectors.

Let’s take the example of automotive. Owning the ability to differentiate is the key to success in such a rapidly evolving sector. Players in this industry will need best-in-class quality IP but also processor design automation technology with the potential to accelerate innovation through processor customization. Jamie Broome, our VP of Automotive, wrote an interesting article on the potential of RISC-V and customization for automotive.

5. THE RISC-V ECOSYSTEM IS GROWING RAPIDLY

The RISC-V standard is maintained by RISC-V International, with members such as Codasip, coming from across the industry: software, systems, semiconductor and IP. The focus is on building a rich hardware and software ecosystem, and this is happening. RISC-V International mentions more than 3,100 RISC-V members across 70 countries.

There have been new processors and new ISAs in the past. But what is different about RISC-V is the ecosystem. As both Intel and Arm have shown, this is the critical factor in a processor architecture’s success. More ecosystem players means more software, more tools: that means more developers selecting that ISA, more commercial traction, which in turn attracts more ecosystem partners in an accelerating virtuous spiral. It is that spiral that is driving the market success of RISC-V.

Did you hear about the Intel® Pathfinder for RISC-V program? Or the OpenHW Group? From creating development environments to starting your RISC-V journey to make verification a real strength, the ecosystem is growing and evolving rapidly to make RISC-V the preferred choice of the majority.

RISC-V is for all. That’s the great thing about it. And with more players, from tools and IP providers to adopters, there is only more choice which can only lead to greater innovation. We, at Codasip, are very excited to be part of the revolution.

If you want to stay informed, simply join our community! We regularly share the latest news and achievements in our newsletter.

Join the Codasip RISC-V community

Filip Benna

Product manager

Collaboration leading the way for broad RISC-V adoption


September 12, 2022

We recently announced a partnership with Intel as part of the launch of the Intel® Pathfinder for RISC-V, making leading RISC-V technology more accessible for prototyping, production design or research purposes using Intel FPGAs.

Intel Pathfinder for RISC-V allows for a variety of RISC-V cores and other IP to be instantiated on FPGA platforms, with the ability to run industry-leading operating systems and toolchains within a unified IDE. By providing a common environment for accessing RISC-V and peripheral IP, Intel is enabling SoC architects and system designers to assemble and test different IP combinations in a single environment.

The launch of the Intel Pathfinder for RISC-V program is an attestation of the commitment to RISC-V from the world’s leading semiconductor manufacturer, and it serves as tangible evidence of what has been expected to happen: the RISC-V ecosystem is maturing rapidly, and Codasip is recognized a key player of that ecosystem.

Image source: Intel. Read Intel’s press release here.

LEAPING FORWARD TOGETHER

The ecosystem around RISC-V is still young and have in some ways been considered too scattered, too immature. But so far in 2022, the ecosystem has taken a number of huge leaps forward. For example, Intel made a series of announcements at the beginning of the year and additional semiconductor companies have joined as members of RISC-V International. At Embedded World 2022, Max Maxfield of EE Journal was impressed by the amount of activity generated by the RISC-V ecosystem, he explains why in the article “RISC-V Takes Embedded World 2022 by Storm”.

Even with all the interest around RISC-V, there have not been that many straightforward solutions available for evaluating and getting hands-on experience from complete systems including cores and peripherals from different vendors in the rich RISC-V ecosystem. Through the collaboration between vendors in the Intel Pathfinder for RISC-V program, SoC designers and system developers can now easily explore different configurations and combinations of IP, including Codasip’s L31 core, in a single environment.

ENABLING A BRAVE NEW WORLD

The award-winning L31 core is a small, efficient 32-bit embedded RISC-V processor core aimed at low-power AI/ML applications such as IoT edge devices. With a 3-stage pipeline, 32 general-purpose registers, and support for Google’s TensorFlowLite for Microcontrollers, the core is designed to support challenging tasks such as neural networks even in the smallest, power-constrained applications.

Our L31 core along with the Intel Pathfinder for RISC-V program lets you kickstart your next RISC-V project and start exploring options. Once you have found a good setup for your design, you can move into production by licensing from Codasip the same off-the-shelf L31 core that you evaluated through the program. This best-in-class quality standard core can perfectly match your needs, but you could also customize it to fit your unique, specific application. IoT edge devices are typically resource-constrained and there is much to gain from customizing the core for the specific application requirements. The customization can be managed in a very straightforward way using Codasip Studio, a unique collection of tools for automated design or modification of processors.

The openness of RISC-V offers unique potential for innovation and customization. Intel’s evaluation platform, co-developed with leading RISC-V vendors like Codasip, will certainly increase the rate of RISC-V adoption. As a founding member of RISC-V International, Codasip can only applaud the initiative. A brave new world of heterogenous computing and domain-specific accelerators is open for exploration. Try it and see for yourself! Go to pathfinder.intel.com to start exploring.

Learn more about the Codasip and Intel partnership

Mike Eftimakis at Codasip

Mike Eftimakis

DAC 2022 – Is it too risky not to adopt RISC-V?


July 18, 2022

I was fortunate enough to attend the 59th Design Automation Conference (DAC) in San Francisco last week. Aside from the Covid closure in 2020 I’ve been going to DAC since 1995. Many people, including me, arrived to the San Francisco with a bit of trepidation. After all, 58th DAC had low attendance and it was only ~7 months ago. What was the DAC 2022 conference going to be like? How would Covid affect things? Would international travelers come to San Francisco?

Frankly, I was impressed! Yes, the exhibit hall is smaller than it used to be. Yes, the attendance is not what it was in the 2000’s… and yes, there were times where it was quite slow on the exhibit floor. At the end of the day the many international travellers did show up and the conference and exhibits were quite well attended. At Codasip we met with customers and prospects from all over the world — Korea, Japan, Europe, the US, and more.

The Codasip team at our booth
The Codasip team at our booth  

Moore’s Law continues to slow

I started the week on Sunday at the well-attended Needham analyst event with Charles Shi. Charles mentioned there were concerns about a semiconductor down cycle but thought that the EDA and IP companies could push through without too much trouble. Charles expanded on his talk from December 2021 noting that Moore’s Law continues to slow and this is, at least partially, driving wafer and transistor costs higher as transistor density is no longer doubling in each new node.

I latched onto a comment that Charles made — that leading systems companies were designing their own chips. Companies like Apple, Tesla, and others were beating Moore’s Law and differentiating their product by building their own custom chips.

Slide from Charles Shi's talk - System providers designing their own custom chips
Slide from Charles Shi’s talk – System providers designing their own custom chips

If scaling is no longer an option in most situations, optimization means customizing a processor for your specific application. The only way forward to differentiate is architectural innovation. If you haven’t already, I encourage you to look at our whitepaper on semiconductor scaling.

The demo at our booth showing the benefits of adding custom instructions on our L31 RISC-V core raised a lot of interest

The demo at our booth showed what Jon Taylor, our Director of Application Engineering, presented at Embedded World 2022 on customizing RISC-V cores to accelerate neural networks. You can watch his talk here.

Optimism around the industry, RISC-V, and Codasip

One of the highlights of my week was the executive dinner hosted by the Codasip management team. The intimate event included customers, partners, and industry supporters. We shared ideas, told stories, and had a lot of laughs together. There is nothing quite like having this time in person – the online meetings just can’t compare. One takeaway from that event was the optimism around the industry, RISC-V, and Codasip.

Executive dinner hosted by the Codasip management team

Is it too risky not to adopt RISC-V?

A couple of weeks ago, Embedded World 2022 showed us that the RISC-V genie is now out of the bottle. It was therefore no surprise to see that a key theme of this DAC was RISC-V. RISC-V appeared in papers, posters, presentations, tutorials, and in the exhibit hall. There were new university ideas, cool security projects, open-source and commercial implementations of RISC-V, and verification technologies, to name a few.

The question is no longer if RISC-V is too risky too adopt — but is it too risky not to adopt.

And companies are adopting RISC-V. The RISC-V International community is made up of over 200 companies from 50 countries. A quick search on Indeed.com shows over 400 job postings referencing RISC-V in the US alone. This doesn’t even include the dozens of jobs that Codasip has open!

One very interesting thing we heard at DAC is about John Deere designing their own ASICs to improve customer productivity and help to deliver more value to farmers. The company, by investing in building its internal capabilities around data science and analytics, is transforming into a data-driven technological manufacturing company. The John Deere Operations Center delivers value to farmers with tools and features that enable them to easily access farm information to better manage their daily operations. This article is a nice summary of how John Deere is leveraging AI, IoT and data analytics.

All in all, it was a great week at the Design Automation Conference. I’m certainly looking forward to the 60th DAC in 2023. It was great to see all of the new innovation in the industry and especially around RISC-V. RISC-V is here and the team as Codasip is proud to be leading the way with our unique approach to RISC-V.

Brett Cline

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Closing the Gap in SoC Open Standards with RISC-V


March 24, 2022

The semiconductor industry has changed hugely in the last 3 or 4 decades. Around 1980 some larger semiconductor companies were strongly vertically integrated, not only designed and manufactured their products, but even made their own processing equipment and in-house EDA tools. Today almost every semiconductor company uses 3rd party equipment for IC manufacturing and designs using 3rd party EDA tools and 3rd party IP. A key reason why the disaggregation of the semiconductor industry has happened is the use of open standards.

There is no universally agreed definition of an open standard but it is generally agreed that they are available on a reasonable and non-discriminatory basis. In many cases, especially in SoC design, such standards are available on a royalty-free basis. Many open standards are owned by independent bodies such as the IEEE, OSI and IETF (internet engineering task force) rather than by companies. In such cases the further development of the standard is through an open process with widely-based participation.

Open Standards and SoC Design

It is worth looking at open standards for SoCs from both hardware and software angles. For embedded software, C and C++ have been well-established as open standards. Middleware and real-time operating systems (RTOS) have therefore frequently been supplied as source code using one of these languages. Some porting may be necessary where there are processor- or peripheral-dependencies but generally design teams can tackle this.

In many current devices, especially in IoT, an SoC has either wired or wireless communications. Such links require communication protocols based on open standards such as Ethernet or Bluetooth LE. Such networked devices are also likely to require some sort of security and again open standards enable secure communications.

In digital hardware design, the microarchitecture is described in a hardware description language. Both Verilog and VHDL are IEEE open standards and the RTL description will be synthesized to the gate level. Processors and peripherals are frequently connected by AMBA buses which are a set of standards owned by Arm but available royalty free.

Verification will frequently be done using UVM (Universal Verification Methodology) which again is an open standard managed by the Accellera industry organisation. Power intent can be expressed in UPF (Unified Power Format) – another Accellera standard.

Finally, at the physical design level layout is required for silicon manufacturing. For decades GDSII, originally developed at Calma, has been used as the main interchange format. More recently, OASIS (Open Artwork System Interchange Standard) has been used as an open standard for layout.

The benefits of open standards

Open standards have provided many benefits to industry. Firstly, they have provided interoperability between chips, between software packages and between design tools. This has enabled disaggregation.

Secondly, if there are open standards there is an opportunity for an ecosystem of products and vendors to develop. For example, with C there are a host of software development tools available as well as middleware and RTOS products for embedded software reuse. At the hardware level there is a wide range of EDA tools that use open standards such as Verilog, UVM and OASIS. This means that development teams have a wide choice of vendors and do not need to depend on a single vendor.

Thirdly, an open standard means that one level of specification is already accomplished allowing product companies to focus on differentiation through their implementation.

However, the ‘elephant in the room’ is that there has been an obvious gap in the open standards. The ISA represents the all-important interface between hardware and software, but this has historically been almost exclusively the preserve of proprietary ISAs.

Closing the gap in open standards with RISC-V

With RISC-V there is for the first time a truly open standard for an ISA with real industry support. The ISA combines a very lightweight base integer instruction set with the flexibility of standard and custom extensions. The RISC-V ISA does not specify a microarchitecture so, for example, Codasip has developed RISC-V processor cores with three-, five-  and seven-stage pipelines thus allowing designers to match a core to their needs. IP vendors differentiate with microarchitecture.

An immediate benefit for embedded software suppliers and for SoC developers is that it is attractive to offer middleware as binaries (as well as just source code). This alone should help RISC-V adoption to accelerate by simplifying work for embedded software developers.

Using an open ISA is a catalyst for a rapidly expanding ecosystem embracing processor IP vendors, software development tool providers, software companies and semiconductor companies. Just as in networking, token ring proprietary products were squeezed out by the growing ecosystem of Ethernet around 1990, we can expect proprietary ISAs to be squeezed out by RISC-V in the coming decade.

Lastly for companies developing their own processor cores, the base instruction set is available royalty free. The modularity and extendibility of the RISC-V ISA means that basic instructions are already defined, and the developers can focus on the specific value add of their core or accelerator.

Adopting RISC-V is now a low-risk choice for embedded SoC developers. The crucial gap in SoC open standards has been closed to the benefit of both hardware and software developers.

Roddy Urquhart

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RISC-V Summit 2021


December 17, 2021

We weren’t sure what to expect from our first major attendance at a #RISCVSummit. Although we were a founding member of RISC-V – as we’ve been saying quite a lot recently – we have been hiding our light under a bushel.

We’ve certainly been busy though – enabling over 2 billion RISC-V cores with our RISC-V processor IP and Studio tools while helping customers use architecture licenses, customization and domain specific compute – but perhaps we neglected the publicity.

CTO Zdeněk Přikryl presents RISC-V custom instruction session. Image source: Codasip.

However, we are now growing seriously and we know we can’t rest on our laurels. So off to San Francisco we trotted…A magnificent team of seven Codasippers were at the Summit, including a raft of our senior execs: new CEO Ron Black,  CRO Brett Cline and CTO Zdeněk Přikryl together with a US sales team and more. Mustn’t forget myself: CMO Rupert Baines!

With Omicron timed to spoil the party, the event’s attendance was never going to be the best ever. A lot of visitors sadly did have to cancel. But while numbers were down, there were still a lot of good meetings and great presentations. Interestingly, the Summit was busier than DAC with which it was co-hosted. DAC is of course a fundamentally important event in the design calendar, but it was clear that RISC-V still brings with it a sense of something new and exciting: a growth opportunity. And who doesn’t love a growth opportunity.

For those of us from outside USA it was also a great opportunity to meet customers face-to-face even if they were not at the event. Doing business over Zoom has been efficient but there is something magic that happens with a CTO, a whiteboard and an engaged customer architect.

Meanwhile, Filip enjoyed his first US trip and clocked up his tourist points.

Image source: Codasip.

Ron’s presentation on the end of scaling and need for heterogenous compute was particularly well-received – with plenty of nodding heads in the audience. Watch the video recording of ‘Scaling is Failing’ keynote address here. Ron recently put his thoughts into a blog

Ron Black, CEO. Source: Codasip.

The Summit saw some new entrants into the RISC-V ring. It is great to see the growing interest in RISC-V – although you could say they’re late to a party that’s now well and truly underway! We know from our own experience that there are no shortcuts to catch-up.

There were also new launches from existing RISC-V vendors, but from our perspective nothing that changes our outlook nor our prospects on selling our next 2 billion cores.

Our friends at Imperas were making a very good point on the need for better verification in RISC-V – something we passionately believe in (and it was incredible how some people seem not to appreciate). Watch the Imperas RISC-V verification presentation here.

The fact is, the RISC-V market is ripe for domain specific designs, as Ron made clear from his presentation: Dennard, Moore’s, Amdahl’s,..these traditionally immutable laws of semiconductor design and scaling are, well, mutable!

If you missed the event, watch the presentation from Ron Black, Zdeněk’s 10 minute overview to custom instructions in RISC-V and contact us directly to find out how we can help you design the best possible processors to differentiate your product in an increasingly competitive marketplace.

Rupert Baines

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Is RISC-V the Future?


July 27, 2021

Is RISC-V the future? This is a question that we often get asked, and let’s assume that we mean ‘is RISC-V going to be the dominant ISA in the processor market?’. This is certainly an unfolding situation and has changed significantly in the last five years.

What is RISC-V and what does RISC-V do?

RISC-V originated at the University of California, Berkeley, in 2010 and took a number of years to get traction with industry. A big step forward was the formation of the RISC-V Foundation in 2015 as a non-profit organization to drive the adoption of RISC-V. In early 2020, the RISC-V Foundation activity was re-branded and re-incorporated as the Swiss-based RISC-V International.

I remember exhibiting at Embedded World in 2017 and the Codasip stand had the RISC-V logo prominently displayed. Many visitors asked, “what is RISC-V?”, showing that awareness in Europe was low. Since then, the situation has changed dramatically with a high level of interest in all geographies.

For many years, we have tended to classify processors into silos such as MPU, MCU, GPU, APU, DSP, etc. Some devices, such as mobile phones, would combine multiple types of processor cores in their designs. If we think back to, say, 2016, the MPU world was dominated by the X86 architecture while Arm dominated both APUs (application processors and the mobile phone ecosystem generally) and MCUs.

Is RISC-V better than Arm? Is RISC-V better than x86 from Intel/AMD? It definitely is different and brings new opportunities. Today we can identify a few new trends in the market that RISC-V is enabling. Let’s look at 3 of them.

Trend 1: RISC-V is shifting up in performance

In the early years of RISC-V, it was mainly used on academic projects. However, by 2016 a wide range of commercial companies were developing embedded microcontrollers based on the RISC-V ISA. It could be argued that this was a relatively easy step for the RISC-V community, given that embedded developers are used to building their systems from a variety of sources, including middleware delivered as source code. Also embedded cores are simpler in complexity.

RISC-V processor performance trending upwards. Source: Codasip.

What is more challenging is moving into application processors, with considerably more complexity required to support rich operating systems such as Linux or Android. In the case of mobile phone applications, there is a complex ecosystem which will take a while for RISC-V vendors to support. Nevertheless, there are plenty of other opportunities for RISC-V application processors in systems which use Linux, and there is a choice of IP cores such as Codasip’s A70 addressing mid-range performance.

Finally, we can expect more and more suppliers to create complex RISC-V cores for high-performance computing in the future.

Trend 2: RISC-V is breaking down the barriers between processor types

With semiconductor scaling failing, the boundaries between traditional processor grouping are blurring. With more and more demand for domain specific accelerators to achieve cost-effective performance on-chip, it is more and more necessary to tune the design to the needs of the workload required.

With the RISC-V ISA, having a minimalist base integer instruction set and providing for custom extensions, it is an ideal starting point for creating special accelerators.

While some applications, such as mobile phones, with complex legacy software are unlikely to change architecture in the short term, others have no constraints. New applications, such as  AI (artificial intelligence), are moving to RISC-V as the open ISA with flexibility and customization. And in a more distant future, RISC-V has the potential to gain even greater market share as legacy considerations cease to apply.

Trend 3: Customers want to avoid a monopoly supplier

Finally, there is a strong desire for change in the processor market. Since the 1980s, microprocessors have been dominated by the Intel/AMD X86 duopoly, but in the late 1990s, Arm became the de-facto standard in the mobile phone processor market. That monopoly extended further into adjacent areas, including embedded.

For the last decade, I have often heard engineers talk of “Arm fatigue” and disquiet with the monopolist position and vendor lock-in in key markets. However, as long as Arm could claim ‘Swiss neutrality’ with their broad product range, nobody would be fired for licensing Arm. With their acquisition by SoftBank, that neutrality was seriously eroded, and the now failed Nvidia merger attempt unsettled many licensees.

The free and open RISC-V ISA has seen widespread interest and is likely to be a catalyst for a sea change in the market. As an open standard, it has the potential to be relevant for decades, and with multiple suppliers offering processor cores, it avoids vendor lock-in.

RISC-V shipments predicted to grow strongly. Source: Semico Research Corporation.

While nobody expects architectures with a rich history – such as X86 or Arm – to disappear overnight, for the first time in decades designers have a viable alternative in RISC-V. With RISC-V covering a greater and greater range of performance and having a rapidly expanding ecosystem, the market share for RISC-V will continue to grow. This is reflected by market reports such as Semico Research, predicting that the market will consume 62.4 billion RISC-V CPU cores by 2025.

RISC-V surely has a rapidly growing future and a great chance of being a dominant architecture.

Roddy Urquhart

Roddy Urquhart

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What does RISC-V stand for?


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RISC-V stands for ‘reduced instruction set computer (RISC) five’. The number five refers to the number of generations of RISC architecture that were developed at the University of California, Berkeley since 1981. It is pronounced “risk-five” and you might sometimes see it written “RISC five“ or “R5“).

The RISC concept (like the parallel MIPS development in Stanford University) was motivated by the fact that most processor instructions were not used by most computer programs. Thus, unnecessary decoding logic was being used in processor designs, consuming unnecessary power and silicon area. The alternative was to simplify the instruction set and to invest more in register resources.

The RISC I project implemented a mere 31, 32-bit instructions but 78 registers. It introduced the notion of register windowing which was a technique that was later adopted by the SPARC architecture. This was closely followed by the RISC II project which had an even larger register file (138 registers). RISC II also introduced 16-bit instructions which improved code density. The terms RISC III and RISC IV have been used to refer to the SOAR and SPUR projects in 1984 and 1988, respectively.

The RISC-V project was partly motivated by the fact that proprietary, closed ISAs were restricted by patents and license agreements. Krste Asanović of the University of California, Berkeley was convinced that there were great advantages in having a free, open ISA that could be applied to both academic and industrial projects. David Patterson, who had worked on earlier RISC projects, was also involved. In 2010, a 3-month project led to the development of a new instruction set, leading to the publication of the first RISC-V ISA specification in 2011.

In order to manage contributions from other parties, the RISC-V Foundation – now RISC-V International – was formed in 2015 as an open collaborative community, and the original developers of the ISA transferred their rights around RISC-V to this organization. Since then, RISC-V International has managed further development of the RISC-V ISA.

Roddy Urquhart

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Does ISA ownership matter? A Tale of Three ISAs


December 22, 2020

An instruction set architecture (ISA) is crucial to the development of processors and their software ecosystems. In the last half century, the majority of ISAs have been owned by single companies, whether product companies for their own chips/systems or processor IP companies who licensed their processors to chip developers. Does ISA ownership matter? Let’s consider three proprietary ISAs and their history.

Firstly, the Alpha ISA was developed by Digital Equipment Corporation (DEC) for its workstations and servers and was released in 1992. In the mid-1990s, this was considered a worthy competitor to SPARC and MIPS RISC architectures. However, the ownership of the ISA transferred to Compaq when DEC was acquired in 1998. Compaq in turn sold the rights to the Alpha ISA to Intel in 2001, and in the same year Compaq was acquired by Hewlett Packard. The last Alpha-based products were released in 2004, meaning that the ISA was effectively dead because of a series of acquisitions.

MIPS Technologies was spun out of Silicon Graphics as an independent IP company in 1998. For some years it enjoyed some success, particularly at the higher end of the processor IP market, and was only the second architecture to have Android ported in 2009. However, with a declining share price, MIPS sold 498 patents to AST and agreed to an acquisition by Imagination Technology in 2013. After Canyon Bridge acquired Imagination, MIPS was spun-out again ending up, after a series of transactions, as part of Wave Computing. As an artificial intelligence silicon provider, Wave is a potential competitor to some MIPS licensees.

Wave tried to encourage the adoption of the MIPS ISA in competition to RISC-V through their MIPS Open Initiative in late 2018. However, the licensing terms contained some onerous conditions relating to patents. In late 2019, Wave suddenly shut down the program, giving zero notice. The important lesson is that even if an ISA is open, its future is not secure if it is commercially owned. Seven years of ownership change have seen MIPS’ market share spiral downwards.

The third example is Arm, the biggest processor IP company of them all. Arm has long been seen as not only a big, successful IP company, but one offering “Swiss neutrality” in the semiconductor industry. Arm was quite distinct from both semiconductor companies and EDA companies. As such, it enjoyed a position of trust from its licensees as it did not have a conflict of interest. With its acquisition by SoftBank in 2016, Arm lost control over its destiny, even though SoftBank was not competing with its licensees. With the planned acquisition of Arm by NVIDIA, announced in September 2020, Arm will lose its neutrality completely. As a semiconductor company, there is a conflict of interest between Arm’s owners and its licensees, meaning it can no longer be trusted in the same way.

As can be seen from the ‘Tale of three ISAs’, the ownership of an ISA matters a lot, regardless of whether the ISA is commercially licensed or open. Acquisitions can lead to the disappearance of an ISA through merging of product lines or through making licensing difficult. Another motive for taking over a company can even be to kill off a competing product line, which in the case of an ISA could catastrophically impact licensees.

ISA ownership is one of the key issues that the developers of RISC-V have thought about. By transferring the ownership of the ISA to RISC-V International, the original developers of the ISA have assured its longevity. Longevity is assured both by the independent ownership of the ISA and the fact that licensees have a choice of IP vendors supporting the same open standard. Thirdly, once ratified, the ISA is frozen assuring software developers that their code will be able run on suitable cores indefinitely.

Roddy Urquhart

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