Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

Being a design verification engineer is fun and rewarding


November 21, 2022

Philippe Luc, Director of Verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer.

On one hand the UKESF encourages young people to study electronics and pursue careers in this sector, and on the other hand Codasip is very keen to help prepare the engineers who will solve tomorrow’s technology challenges. Philippe’s talk was very well welcomed and we felt we should share it more broadly. If you are a student and wondering what to do next, this blog and his talk are for you.

Here is a sneak peak at the webinar, which we summarized for you in this blog.

Being a verification engineer is fun

In Philippe’s mind, being a verification engineer is fun. There is no daily routine, each project you work on is different, and each bug you find has its own story. What makes a good engineer is their ability to solve problems that never existed before. That’s even more true for verification engineers. This is something that you learn at school, but also throughout our career. Scratching your head, connecting the dots, finding the best ways to ensure quality through innovative techniques, there is no way you can get bored in your job. 

Being a verification engineer is rewarding

From processors in smartphones to smart cards and small embedded devices in your home, it is very rewarding to, one day, have in your hands a product you worked on.

But even before this happens, being a verification engineer is rewarding. If a design verification engineer has the luxury to take a specification and turn it into a quality, cost-efficient, energy-efficient, performant product that is ready when the market needs it, a verification engineer has the power to prove that all of the above works in every single situation, regardless of the configuration, program that is running, external environment, etc. 

Without the design – there is no product. Without verification of the design – there is no product either, it wouldn’t fit the quality requirement of any customer.

Did you know that Codasip has a University Program? Cooperation between Codasip and academia accelerates development of RISC-V processor IP, electronic design automation, and verification tools and methodologies.

What makes a good verification engineer

As mentioned before, a good verification engineer can solve problems that never existed before. In other words, what makes a good verification engineer is the right mindset. But, let’s not give away too much in this article. Philippe tells you more in the webinar linked at the bottom of this page. 

Verification engineers have a bright future

In the 1980s, we could count approximately one computer for 100 households. In the 2000s, it became one computer per household. Today, there are at least 10 processors just in your pocket! – and of course a lot more in the household now.

The electronics market is growing and evolving. Will our job still exist in 20, 30, 40 years? Based on today’s digital world, yes. Everything includes at least one processor. Smartphones, music players, cameras, earbuds, door bells, coffee machines, light bulbs, you name it. The technology will change, as we have seen it in the past, but the skillset students are gaining today will be similar. 

What’s next? 

If this blog post made you consider a career as a verification engineer, you should watch the full webinar where Philippe shares a lot more details and insights.

And then, have a look at our careers page – your future as a verification engineer may be with us at Codasip!

Lauranne Choquin

Corporate Marketing Manager

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Single unified toolchain empowering processor research


May 23, 2022

The RISC-V’s open Instruction Set Architecture (ISA) has spurred the innovation of free software tools and application software. Many of these software developments are software “islands” that must be combined through scripts. With different tools from different sources, continual interoperability is at risk and there is a support cost of monitoring and updating their interoperability. The alternative is a single unified toolchain. The benefit of the unified approach is twofold. First, the obvious case in that the toolchain upgrades are validated before releases ensuring a functional toolchain reducing or eliminating the required monitoring of different tools and upgrading required scripts. The second benefit is not as obvious but may be the most important: through a single unified toolchain, researchers benefit from enhanced tools.

The Codasip’s University Program makes available Codasip Studio, a single unified for processor architecture’s ISA specifications, development of the processor’s hardware architecture, software development tools, to outputting RTL such as Verilog for FPGA and ASIC synthesis. The University Program has been developed to spur innovation in research and student curriculum. Let’s see, in this blog post, how Codasip Studio will benefit researchers and engineering students.

Single unified toolchain for processor development

Codasip Studio outputs a Hardware Development Kit (HDK) and a Software Development Kit (SDK).  The HDK includes all the tools and tasks to specify a processor’s Instruction Accurate (IA) model and implement it as a Cycle Accurate (CA) model.  These models are specified using CodAL, a C-like processor description language that enables high-level synthesis description of both the IA and CA models. The SDK includes all the tools required for software application development starting at the assembler to linker, to C-compiler, to C-libraries, through software simulator.

As the status of these integrated development tools is aware of each other, as in a makefile software build, only the required tasks are built. For example, if you modify a file that changes the IA model and is shared with the CA model, all the tasks for both the IA and CA model will be marked as not built. Upon requesting a higher-level task to be built, all lower dependent tasks that are not built will be built first. A good example is the SDK (IA) task.  If this task is built, all dependent tasks such as Model Compilation, Assembler, Disassembler, Profiler, Simulator, Debugger, C/C++ compiler, and SDK libraries will be built if necessary. No script development or toolchain maintenance required.

Enhanced tools through a Unified Toolchain

How can Codasip Studio’s unified toolchain enhance research?  Tightly coupling application integration with program acceleration into a processor’s core is a new research domain. To make engineering decisions, data is required. Codasip Studio’s integrated Profiler can analyze a software application to determine where clock cycles are spent, enabling researchers to focus where new instructions can result in program acceleration through cycle count reduction.

Snapshot of Codasip Studio

As in this example, the profiler annotates the C-program to highlight where clock cycles are spent, and the associated assembly sequence. The Researchers can minimize the original sequence into a single new instruction with the objective of not elongating the clock period.

RISC-V generated compiler realizes instruction acceleration

Creating new instructions for acceleration remains in the hypothetical sphere until it can be incorporated into useful applications. Codasip Studio compiler’s input is the processor’s IA model.  Analyzing data from the profiler, researchers define a new instruction into the processor’s ISA, and upon rebuilding the SDK (IA), a compiler will be aware of the new instruction and use it in subsequent program builds.

From the program disassembly above, the newly added instruction has been incorporated into the compiler to replace the original two RISC-V instructions. Application acceleration has been achieved through cycle count reduction. The program cycle count can also be verified through running the updated program through the Profiler.

The entire process from initial application profiling, minimizing the instructions, to implementing a new instruction into the IA and CA models, and verification of program cycle count reduction can be achieved in an hour or two. The unified toolchain enables a very tight loop from data to concept to experimentation. With these short development cycles, researchers can easily experiment to find the optimal solution.

Get started with the University Program to explore Codasip Studio’s unified toolchain and how it can benefit your research in Program Security, Functional Safety, Artificial Intelligence, Real-Time Embedded Systems and other Domain Specific Architectures.

Learn more about the Codasip University Program

Keith Graham

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With closed processor Instruction Set Architectures (ISA) with limited access to processor Intellectual Property (Arm and x86), university professors have often limited their research to two main spheres: optimizing software algorithm(s) and external hardware. University researchers have not been able to consider optimizing the processor due to the lack of access to processor Intellectual Property (IP).   Where these two spheres overlap, trade-offs are made to optimize the solution. A conventional research barrier is the exclusion of processor architecture optimization. Coprocessors or external accelerators can be explored, but they are limited and costly in solving tomorrow’s technological challenges in Processor Security, Functional Safety, Intelligent Memories, and Artificial Intelligence.

We launched the Codasip University Program in March 2022 to support you, engineering professors and students, and advance technology that will solve tomorrow’s technological challenges. Because of Moore’s Law and Dennard’s Scaling challenges, computer architects have developed solutions through integrating multiple homogenous and heterogenous cores. Tightly coupling application acceleration and application-specific requirements into the processor core is a new research domain to solve tomorrow’s computational needs. Let see, in this blog post, how you can jump start on this opportunity with our program.

University research is often limited to hardware and software optimization

Conventional research has been limited to software algorithms and external hardware resources due to fixed and closed processor architectures. Unfortunately, an important component of the research equation – the processor – has been left out.

Processor architecture optimization is excluded from university research

Let’s start with an example. Sequential memory elements such as register files and pipeline registers are not commonly protected against single bit upsets that may occur via an alpha particle or a security attack. To protect from these upsets, external processor monitors or a 1 out of 2 voting strategy can be considered, but greatly increasing the design and validation complexity at increased cost.

Optimizing the processor architecture itself is missing from the above solutions. Three elements are now available to you through the Codasip University Program to break through this barrier and to include tightly coupling the application’s requirements into the processor.

RISC-V and Codasip Studio made available to university researchers to break through the processor architecture optimization barrier

With access to RISC-V cores and Codasip Studio, you, university researchers and students, can now explore new processor architectures that integrate application-specific features and acceleration – and ultimately become tomorrow’s solutions and engineers.

Breaking through the research barrier to include processor architecture optimization

With RISC-V IP and Codasip Studio, resources can now be brought into the processor for optimization and solution trade-offs can occur between all three spheres.

Processor architecture optimization included in university research

Continuing our single bit upset example, can we solve this fault by integrating a solution into the processor to protect its memory and register bits?

Architectural optimization through application-specific integration into the core

Processor architecture optimization involves two key concepts:  tightly coupling application-specific functionality into the processor and enhancing the processor performance through cycle-count reduction.

Using Codasip Studio and RISC-V cores, you can add Hamming encoding to write to the register file and decoding upon reads. The register file is now protected through two-bit error detection and single-bit error correction (ECC) by developing functions in the processor’s Cycle Accurate (CA) model using CodAL.

CodAL is an architectural high-level description language that describes the processor’s ISA (Instruction Accurate (IA) model) and the hardware implementation (Cycle Accurate (CA) models). Pipeline registers can be protected with parity to provide real-time bit error detection. When a fault is detected, the parity checker can assert a processor exception for handling. ECC and parity can be extended to either the L1 or L2 caches.

For a set of applications, would integrating the processor into solving single bit upsets reduce design complexity, development and validation time, as well as solution cost? Applications can be accelerated by reducing program clock cycles assuming the clock frequency remains constant. Using Codasip Studio’s profiler, you can analyze the most common sequence of operations to replace two or more RISC-V instructions with a single new instruction. Using CodAL to update both the IA and CA models, this new instruction becomes available to the application developer through Codasip Studio’s assembler and C-compiler.

Explore new research avenues with the Codasip University Program

Empowering processor architecture optimization enables you to imagine new avenues of research that was not feasible before. Here are just three possibilities…

Empowering processor architecture optimization brings new possibilities for researchers

Get started with the Codasip University Program to explore new processor architecture optimizations through integrating application-specific functionality and acceleration.

Keith Graham

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Keith Graham has been appointed to lead the new Codasip University Program. From helping tomorrow’s processor experts to developing the technologies that will solve tomorrow’s technical challenges, and accelerating innovation, we asked Keith what it is all about. Keith explains how the University Program will help today’s engineering students become the next generation of processor engineers our industry needs.

Keith, why did you accept to join and lead the Codasip University Program?

Becoming the Head of Codasip’s University Program is my dream job. The technological challenges of tomorrow are yet to be solved and the next generation of processor engineers will need innovative, best-in-class IP and technology to achieve this. Before joining Codasip, I was already convinced by the benefits of customizing RISC-V processors using Codasip’s unique technology. Having many years of experience developing courses for the University of Colorado, it felt obvious to me that Codasip and universities could do great things together.

Over my thirty-seven years upon graduating Penn State, I have been a hardware design engineer, worked in start-ups, sold semiconductors, a small business owner, and a senior instructor at the University of Colorado at Boulder. It is time for me to give back to the next generation.

What was the idea behind developing research partnership with universities?

In the 1980s, it was an era that it was not difficult to find a company that was developing a custom processor, but it ended due to the need to standardize software. The number of mainstream processors narrowed to around 6 in the 1990s. Now, with the open architecture of RISC-V, it solves the issue of standardized software with the advantage of enabling processor customization.

To solve tomorrow’s technology challenges in security, artificial intelligence, and many other domain specific applications, we need a new generation of processor engineers.

We are at the start of a new golden age of processor designs. Through the University Program, we will be making available innovative curriculum material, supporting research faculty, and creating an ecosystem to spur innovation and product development.

Keith Graham. Head of University Program. Source: Keith Graham.

What can engineering students and researchers expect from the program?

The Codasip University program helps universities develop the theory and the design skills that companies developing tomorrow’s SoCs will need. Together with our technology partners we provide engineering students and researchers with the support they need for their research projects.

Students and researchers will be provided with computer engineering curriculums, assignments, materials, and industry-grade tools.

By partnering with universities, we create a Design for Differentiation Ecosystem that will encourage sharing of knowledge, experiences, ideas and designs. Universities will have access to FAQs, knowledge boards, a design database to share solutions, and will be able to participate in community activities such as design contests.

Which Codasip technology will students and researchers have access to?

The support of both the students and researchers will be through Codasip unique design automation toolset Codasip Studio and our High-Level Synthesis Language CodAL.

It is essential to provide students with access to CodAL and Studio. This unique technology will enable them to focus on becoming innovative processor designers. CodAL, our patented architecture description language, is more efficient and less error prone compared to using a less abstracted language like Verilog. Perfect for students.

With Studio, we want to provide the ideal processor design automation platform that will help future SoC designers build their ideas into something that could become a commercial product.

Interested in the Codasip University Program? Learn more on our website and get in touch with us.

Lauranne Choquin

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