Learn how to choose a processor IP core to best fit your needs in this 24-page e-book.
This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers.
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The RISC-V ISA is designed in a modular way, meaning that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows implementing precisely the instruction groups that the domain needs, without having to pay for area or power that will not be used.
Mythic, the provider of a unique AI compute platform, was designing an innovative intelligence processing unit (IPU) and found themselves in need of a very specific core that was not available on the market. Mythic created it in Codasip Studio, starting from the off-the-shelf Codasip Bk3 core, and got their optimized domain-specific core without compromises or delays.
Learn how to use Questa® SLEC, the formal analysis app from Mentor, to compare a fully UVM-verified HDL code with a new HDL output, making sure that they are functionally identical – in a fraction of the time needed before.
Jump threading is a type of compilation optimization that aims to produce faster code. Codasip introduced its own implementation of jump threading in its LLVM-based compiler that is a part of Codasip’s unique tool suite, Codasip Studio. Our latest whitepaper describes how the implementation works and how it can be used to improve speed of a program execution, earning better benchmarks along the way.
Learn how to incorporate Questa® VIP into your existing RISC-V verification flow. The tutorial, prepared by Codasip’s verification experts, explains the concepts of combining automatically generated UVM with QVIP and guides you through the process.
