Blog
Check out the latest news, posts, papers, videos, and more!
What's New in Codasip

20 Jul, 22
Blog
by Lauranne Choquin
A Codasip Greece Design Center to extend leadership in Europe

18 Jul, 22
Blog
by Brett Cline
DAC 2022 – Is it too risky not to adopt RISC-V?

07 Jul, 22
Blog
by Lauranne Choquin
Processor design automation to drive innovation and foster differentiation

28 Jun, 22
Blog
by Roddy Urquhart
Embedded World 2022 – the RISC-V genie is out of the bottle

23 May, 22
Blog
by Keith Graham
Single unified toolchain empowering processor research

16 May, 22
Blog
by Rupert Baines
Design for differentiation: architecture licenses in RISC‑V

05 May, 22
Blog
by Jamie Broome
Building the highway to automotive innovation

02 May, 22
Blog
by Keith Graham
Processor architecture optimization is not a barrier for university researchers

29 Apr, 22
Blog
by Philippe Luc
Building a Swiss cheese model approach for processor verification

04 Apr, 22
Blog
by Philippe Luc
Measuring the complexity of processor bugs to improve testbench quality

24 Mar, 22
Blog
by Roddy Urquhart
Closing the Gap in SoC Open Standards with RISC-V

16 Mar, 22
Blog
by Lauranne Choquin
How Today’s Engineering Students Will Become the Processor Engineers of Tomorrow

14 Mar, 22
Blog
by Philippe Luc
Improve Your Verification Methodology: Hunt Bugs Flying in Squadrons

10 Mar, 22
Blog
by Emmanuel Till-Vattier
A European Opportunity for Codasip

07 Mar, 22
Blog
by Philippe Luc
4 Types of CPU Bug You Should Pay Attention To

03 Mar, 22
Blog
by Lauranne Choquin
Three Reasons why Codasip Women Engineers are Awe-inspiring

28 Feb, 22
Blog
by Philippe Luc
Why Codasip Cares About Processor Verification – and Why you Should too

18 Feb, 22
Blog
by Rupert Baines
How to extend the ‘unscalable’ RISC architectures

17 Dec, 21
Blog
by Rupert Baines
RISC-V Summit 2021

02 Dec, 21
Blog
by Ron Black
Scaling to new heights at Codasip

01 Oct, 21
Blog
by Roddy Urquhart
Why and How to Customize a Processor

13 Sep, 21
Blog
by Rupert Baines
Why it’s the perfect time to join Codasip and be part of the RISC-V revolution

12 Aug, 21
Blog
by Roddy Urquhart
What is the difference between processor configuration and customization?

27 Jul, 21
Blog
by Roddy Urquhart
Is RISC-V the Future?

21 May, 21
Blog
by Roddy Urquhart
Domain-Specific Accelerators

16 Apr, 21
Blog
by Roddy Urquhart
What is an ASIP?

17 Mar, 21
Blog
by Roddy Urquhart
What does RISC-V stand for?

26 Feb, 21
Blog
by Roddy Urquhart
What is CodAL?

11 Feb, 21
Blog
by Roddy Urquhart
Customizing an Existing RISC-V Processor
29 Jan, 21
Blog
by Roddy Urquhart
How to Choose an Architecture for a Domain-Specific Processor
22 Dec, 20
Blog
by Roddy Urquhart
Does ISA ownership matter? A Tale of Three ISAs

26 Nov, 20
Blog
by Roddy Urquhart
Open Source vs Commercial RISC-V Licensing Models

12 Nov, 20
Blog
by Roddy Urquhart
When Considering Processor PPA, Don’t Forget the Instruction Memory

15 Oct, 20
Blog
by Roddy Urquhart
What is needed to support an operating system?

10 Sep, 20
Blog
by Roddy Urquhart
What is processor core complexity?

20 Aug, 20
Blog
by Roddy Urquhart
Understanding the Performance of Processor IP Cores
22 Jul, 20
Blog
by Roddy Urquhart
Codasip’s Expanding RISC-V Offering
04 Jun, 20
Blog
by Roddy Urquhart
What is SweRV Core EH2?
06 May, 20
Blog
by Roddy Urquhart
More than Moore with Domain-Specific Processors
17 Apr, 20
Blog
by Roddy Urquhart
The Challenges of Making Open-Source RISC-V Deployment Effective
09 Apr, 20
Blog
by Roddy Urquhart
Have you checked the hidden costs of deploying an open source RISC-V core?

08 Aug, 17
Blog
by Roddy Urquhart
Does RISC-V mean Open Source Processors?
21 Jun, 17
Blog
by Karel Masařík
A Tale of Two Approaches to High-Performance IoT

22 Sep, 16
Blog
by Karel Masařík
What is RISC-V? Why We Care and Why You Should Too
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