A Codasip Greece Design Center to extend leadership in Europe

DAC 2022 – Is it too risky not to adopt RISC-V?

Processor design automation to drive innovation and foster differentiation

Embedded World 2022 – the RISC-V genie is out of the bottle

Single unified toolchain empowering processor research

Design for differentiation: architecture licenses in RISC‑V

Building the highway to automotive innovation

Processor architecture optimization is not a barrier for university researchers

Building a Swiss cheese model approach for processor verification

Measuring the complexity of processor bugs to improve testbench quality

Closing the Gap in SoC Open Standards with RISC-V

How Today’s Engineering Students Will Become the Processor Engineers of Tomorrow

Improve Your Verification Methodology: Hunt Bugs Flying in Squadrons

A European Opportunity for Codasip

4 Types of CPU Bug You Should Pay Attention To

Three Reasons why Codasip Women Engineers are Awe-inspiring

Why Codasip Cares About Processor Verification – and Why you Should too

How to extend the ‘unscalable’ RISC architectures

RISC-V Summit 2021

Scaling to new heights at Codasip

Why and How to Customize a Processor

Why it’s the perfect time to join Codasip and be part of the RISC-V revolution

What is the difference between processor configuration and customization?

Is RISC-V the Future?

Domain-Specific Accelerators

What is an ASIP?

What does RISC-V stand for?

What is CodAL?

Customizing an Existing RISC-V Processor

How to Choose an Architecture for a Domain-Specific Processor

Does ISA ownership matter? A Tale of Three ISAs

Open Source vs Commercial RISC-V Licensing Models

When Considering Processor PPA, Don’t Forget the Instruction Memory

What is needed to support an operating system?

What is processor core complexity?

Understanding the Performance of Processor IP Cores

Codasip’s Expanding RISC-V Offering

What is SweRV Core EH2?

More than Moore with Domain-Specific Processors

The Challenges of Making Open-Source RISC-V Deployment Effective

Have you checked the hidden costs of deploying an open source RISC-V core?

Does RISC-V mean Open Source Processors?

A Tale of Two Approaches to High-Performance IoT

What is RISC-V? Why We Care and Why You Should Too