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Check out the latest news, posts, papers, videos, and more!

What's New in Codasip

Check out the latest news, posts, papers, videos, and more!
Codasip team at our booth at Embedded World 2022

28 Jun, 22

Blog

by Roddy Urquhart

Embedded World 2022 – the RISC-V genie is out of the bottle

Codasip Studio will empower processor research through Codasip University Program

23 May, 22

Blog

by Keith Graham

Single unified toolchain empowering processor research

black and white chip design to illustrate a blog on RISC architectures

16 May, 22

Blog

by Rupert Baines

Design for differentiation: architecture licenses in RISC‑V

building the highway to automotive innovation with Codasip

05 May, 22

Blog

by Jamie Broome

Building the highway to automotive innovation

dark and green abstract background

02 May, 22

Blog

by Keith Graham

Processor architecture optimization is not a barrier for university researchers

3 slices of cheese handing

29 Apr, 22

Blog

by Philippe Luc

Building a Swiss cheese model approach for processor verification

processor complexity is measured with scores, like in a vintage game

04 Apr, 22

Blog

by Philippe Luc

Measuring the complexity of processor bugs to improve testbench quality

Closing gap in open standards with RISC-V

24 Mar, 22

Blog

by Roddy Urquhart

Closing the Gap in SoC Open Standards with RISC-V

Codasip Univerdity program for engineering students and researchers

16 Mar, 22

Blog

by Lauranne Choquin

How Today’s Engineering Students Will Become the Processor Engineers of Tomorrow

Verification methodology to hit CPU bugs flying in squadrons

14 Mar, 22

Blog

by Philippe Luc

Improve Your Verification Methodology: Hunt Bugs Flying in Squadrons

RISC-V Europe and EMEA opportunity for Codasip

10 Mar, 22

Blog

by Emmanuel Till-Vattier

A European Opportunity for Codasip

4 red insects represent 4 types of CPU bug

07 Mar, 22

Blog

by Philippe Luc

4 Types of CPU Bug You Should Pay Attention To

A woman engineer touching a blue screen

03 Mar, 22

Blog

by Lauranne Choquin

Three Reasons why Codasip Women Engineers are Awe-inspiring

Electronic circuit with a breakfast in background to illustrate that good processor verification means quality and peace of mind

28 Feb, 22

Blog

by Philippe Luc

Why Codasip Cares About Processor Verification – and Why you Should too

black and white chip design to illustrate a blog on RISC architectures

18 Feb, 22

Blog

by Rupert Baines

How to extend the ‘unscalable’ RISC architectures

Codasip team at RISC_V Summit 2021

17 Dec, 21

Blog

by Rupert Baines

RISC-V Summit 2021

Codasip logo on a chip

02 Dec, 21

Blog

by Ron Black

Scaling to new heights at Codasip

processor customization with Codasip made simpler and faster

01 Oct, 21

Blog

by Roddy Urquhart

Why and How to Customize a Processor

Rupert Baines Codasip CMO Chief Marketing Officer

13 Sep, 21

Blog

by Rupert Baines

Why it’s the perfect time to join Codasip and be part of the RISC-V revolution

A pizza used as example to explain processor customization

12 Aug, 21

Blog

by Roddy Urquhart

What is the difference between processor configuration and customization?

RISC-V logo on a 3-way road

27 Jul, 21

Blog

by Roddy Urquhart

Is RISC-V the Future?

A chip that represents a domain specific accelerator

21 May, 21

Blog

by Roddy Urquhart

Domain-Specific Accelerators

ASIP and application-specific processors to address semiconductor scaling issues

16 Apr, 21

Blog

by Roddy Urquhart

What is an ASIP?

risc-v logo and open source processors

17 Mar, 21

Blog

by Roddy Urquhart

What does RISC-V stand for?

CodAL logo of Codasip architecture language

26 Feb, 21

Blog

by Roddy Urquhart

What is CodAL?

a hand drawing a graph that illustrates customization with RISC-V

11 Feb, 21

Blog

by Roddy Urquhart

Customizing an Existing RISC-V Processor

29 Jan, 21

Blog

by Roddy Urquhart

How to Choose an Architecture for a Domain-Specific Processor

22 Dec, 20

Blog

by Roddy Urquhart

Does ISA ownership matter? A Tale of Three ISAs

a pink pig to illustrate risc-v licensing models

26 Nov, 20

Blog

by Roddy Urquhart

Open Source vs Commercial RISC-V Licensing Models

Abstract CPU on a chip with red connections to illustrate Codasip blog post on processor instruction memory

12 Nov, 20

Blog

by Roddy Urquhart

When Considering Processor PPA, Don’t Forget the Instruction Memory

Abstract blue background with hexagonal shapes to illustrate Codasip blog post on embedded OS support

15 Oct, 20

Blog

by Roddy Urquhart

What is needed to support an operating system?

Abstract CPU on a chip to illustrate Codasip blog post on processor complexity

10 Sep, 20

Blog

by Roddy Urquhart

What is processor core complexity?

Abstract circuit board design to illustrate Codasip blog post on processor performance

20 Aug, 20

Blog

by Roddy Urquhart

Understanding the Performance of Processor IP Cores

22 Jul, 20

Blog

by Roddy Urquhart

Codasip’s Expanding RISC-V Offering

04 Jun, 20

Blog

by Roddy Urquhart

What is SweRV Core EH2?

06 May, 20

Blog

by Roddy Urquhart

More than Moore with Domain-Specific Processors

17 Apr, 20

Blog

by Roddy Urquhart

The Challenges of Making Open-Source RISC-V Deployment Effective

09 Apr, 20

Blog

by Roddy Urquhart

Have you checked the hidden costs of deploying an open source RISC-V core?

risc-v logo and open source processors

08 Aug, 17

Blog

by Roddy Urquhart

Does RISC-V mean Open Source Processors?

21 Jun, 17

Blog

by Karel Masařík

A Tale of Two Approaches to High-Performance IoT

what is risc-v

22 Sep, 16

Blog

by Karel Masařík

What is RISC-V? Why We Care and Why You Should Too


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