Codasip joins OpenHW Group to contribute to RISC-V verification

Codasip joins Intel Pathfinder for RISC-V program

Codasip expands design team to Greece

Codasip adds Veridify secure boot to RISC-V processors

Codasip Studio Mac extends potential to design for differentiation with RISC-V

Codasip L31 customizable RISC-V core is an Embedded World Best in Show

Codasip appoints Mike Eftimakis as VP of Strategy and Ecosystem

Codasip appoints SH Lee to deliver RISC-V innovations to Korean OEMs

Codasip adopts Siemens’ OneSpin tools for formal verification

Codasip appoints Jamie Broome as its Automotive VP

Codasip appoints Japan EDA veteran

Codasip University Program spurs innovation and boosts curriculums

Codasip steps up its focus on Europe and appoints Till-Vattier as EMEA VP

Codasip’s latest RISC-V embedded cores enable AI/ML edge customization 

Codasip appoints Functional Safety VP

Codasip appoints Ron Black as CEO

IAR Systems and Codasip collaborate to enable low-power RISC-V based applications

Codasip adopts Imperas for RISC-V processor verification

Codasip expands ecosystem with XtremeEDA

Codasip appoints Brett Cline to drive company growth worldwide

Codasip Founder Karel Masařík elected to RISC-V Technical Steering Committee

Codasip boosts Studio Processor Design tools with AXI Automation

Codasip Opens UK Design Center Led by Simon Bewick

Codasip Strengthens Senior Leadership: Rupert Baines Joins as Chief Marketing Officer

Mythic Licenses Codasip’s L30 RISC-V Core for Next-Generation AI Processor

Codasip Announces A71X RISC-V Application Core with Dual-Issue Capability

SEGGER and Codasip Announce Cooperation on RISC-V

Codasip Announces FPGA Evaluation Platforms for RISC-V Processor Cores

Codasip Releases a Major Upgrade of Its Studio Processor Design toolset with a Tutorial RISC-V Core

Codasip to Offer Secure Boot Solutions with Veridify Tools

Valtrix and Codasip Cooperate on Verification of RISC-V Systems

Ron Black Joins Codasip as Executive Chairman

Codasip Announces Commercial Add-Ons to SweRV Core® EH1

TianyiHexin Licenses Codasip L30 for Powering Intelligent Wearable Device Solutions

Menta eFPGA and Codasip Announce Technology Partnership

Codasip Announces Three New RISC-V Application Processor Cores Providing Multi-core and SIMD Capability

NeuLinker Licenses Codasip Bk5 and Studio for Powering Innovative AI and Blockchain Solutions

Codasip Announces a New Design Center in France

Codasip Studio and Codasip CodeSpace 8.4 available

Codasip and Metrics Design Automation Announce the Integration of the Metrics Cloud Simulation Platform in Codasip’s RISC-V SweRV Core™ Support Package Pro

Codasip Releases the First Linux-Capable RISC-V Core Bk7 Optimized for Domain-Specific Applications

Codasip Releases the First Linux-Capable RISC-V Core Bk7 Optimized for Domain-Specific Applications

VITEC Licenses Codasip Bk5 Core for Multi-purpose Use in Video Products

Codasip Extends SweRV Support Package to Include Western Digital SweRV EH2 & EL2 RISC-V Cores

Codasip releases Support Package for Western Digital’s first RISC-V SweRV Core

Codasip Studio and Codasip CodeSpace 8.3 available

Codasip Awarded European Union Horizon 2020 Funding for Developing New RISC-V Processors