Press Releases

Read Codasip's official news, hot off the press!
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22 November, 2021
Press Releases
David Marsden

Codasip adopts Imperas for RISC-V processor verification

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04 November, 2021
Press Releases
David Marsden

Codasip expands ecosystem with XtremeEDA

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02 November, 2021
Press Releases
David Marsden

Codasip appoints Brett Cline to drive company growth worldwide

Karel Masařík
28 October, 2021
Press Releases
David Marsden

Codasip Founder Karel Masařík elected to RISC-V Technical Steering Committee

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26 October, 2021
Press Releases
David Marsden

Codasip boosts Studio Processor Design tools with AXI Automation

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21 September, 2021
Press Releases
David Marsden

Codasip Opens UK Design Center Led by Simon Bewick

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09 September, 2021
Press Releases
David Marsden

Codasip Strengthens Senior Leadership: Rupert Baines Joins as Chief Marketing Officer

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10 August, 2021
Press Releases
Lucie Jirakova

Mythic Licenses Codasip’s L30 RISC-V Core for Next-Generation AI Processor

22 June, 2021
Press Releases
Lucie Jirakova

Codasip Announces A71X RISC-V Application Core with Dual-Issue Capability

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22 June, 2021
Press Releases
Lucie Jirakova

SEGGER and Codasip Announce Cooperation on RISC-V

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21 April, 2021
Press Releases
Lucie Jirakova

Codasip Announces FPGA Evaluation Platforms for RISC-V Processor Cores

13 April, 2021
Press Releases
Lucie Jirakova

Codasip Releases a Major Upgrade of Its Studio Processor Design toolset with a Tutorial RISC-V Core

30 March, 2021
Press Releases
Lucie Jirakova

Codasip to Offer Secure Boot Solutions with Veridify Tools

23 March, 2021
Press Releases
Lucie Jirakova

Valtrix and Codasip Cooperate on Verification of RISC-V Systems

16 March, 2021
Press Releases
Lucie Jirakova

Ron Black Joins Codasip as Executive Chairman

09 March, 2021
Press Releases
Lucie Jirakova

Codasip Announces Commercial Add-Ons to SweRV Core® EH1

23 February, 2021
Press Releases
Lucie Jirakova

TianyiHexin Licenses Codasip L30 for Powering Intelligent Wearable Device Solutions

07 December, 2020
Press Releases
Lucie Jirakova

Menta eFPGA and Codasip Announce Technology Partnership

04 December, 2020
Press Releases
Lucie Jirakova

Codasip Announces Three New RISC-V Application Processor Cores Providing Multi-core and SIMD Capability

03 November, 2020
Press Releases
Lucie Jirakova

NeuLinker Licenses Codasip Bk5 and Studio for Powering Innovative AI and Blockchain Solutions

20 October, 2020
Press Releases
Lucie Jirakova

Codasip Announces a New Design Center in France

08 October, 2020
Press Releases
Jakub Svoboda

Codasip Studio and Codasip CodeSpace 8.4 available

05 August, 2020
Press Releases
Lucie Jirakova

Codasip and Metrics Design Automation Announce the Integration of the Metrics Cloud Simulation Platform in Codasip’s RISC-V SweRV Core™ Support Package Pro

21 July, 2020
Press Releases
Lucie Jirakova

Codasip Releases the First Linux-Capable RISC-V Core Bk7 Optimized for Domain-Specific Applications

14 July, 2020
Press Releases
Lucie Jirakova

VITEC Licenses Codasip Bk5 Core for Multi-purpose Use in Video Products

02 June, 2020
Press Releases
Lucie Jirakova

Codasip Extends SweRV Support Package to Include Western Digital SweRV EH2 & EL2 RISC-V Cores

23 April, 2020
Press Releases
Lucie Jirakova

Codasip releases Support Package for Western Digital’s first RISC-V SweRV Core

24 March, 2020
Press Releases
Jakub Svoboda

Codasip Studio and Codasip CodeSpace 8.3 available

18 March, 2020
Press Releases
Lucie Jirakova

Codasip Awarded European Union Horizon 2020 Funding for Developing New RISC-V Processors


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