Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

Codasip RISC-V处理器

[cs_content][cs_element_section _id=”1″ ][cs_element_layout_grid _id=”2″ ][cs_element_layout_cell _id=”3″ ][cs_element_headline _id=”4″ ][cs_content_seo]Codasip RISC‑V Processors\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”5″ ][cs_element_layout_grid _id=”6″ ][cs_element_layout_cell _id=”7″ ][cs_element_headline _id=”8″ ][cs_content_seo]Codasip Processor Cores\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”9″ ][cs_element_text _id=”10″ ][cs_content_seo]Our processor cores are built on RISC-V, a modern open Instruction Set Architecture (ISA) and implemented in Codasip Studio. This means that they are offered either using a conventional licensing model as RTL, testbenches and SDK, or by licensing the CodAL code used to create the core. If you license the CodAL, you can use the core as a quick starting point for your own custom design using our unique Codasip Studio toolset.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”11″ ][cs_element_button _id=”12″ ][cs_content_seo]Discover the benefits\n\n[/cs_content_seo][cs_element_button _id=”13″ ][cs_content_seo]Portfolio at a glance\n\n[/cs_content_seo][cs_element_button _id=”14″ ][cs_content_seo]Evaluate a core\n\n[/cs_content_seo][cs_element_button _id=”15″ ][cs_content_seo]Get a quote\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_row _id=”16″ ][cs_element_layout_column _id=”17″ ][cs_element_testimonial _id=”18″ ][cs_content_seo]The RISC-V instruction set with custom DSP extensions delivers the performance we require while keeping silicon area to a minimum. The best-in-class Codasip Studio development tools enable us to profile our software and find an optimal set of instructions for our application.\n\nJin Park, CTO, Dongwoon Anatech\n\n[/cs_content_seo][/cs_element_layout_column][/cs_element_layout_row][/cs_element_section][cs_element_section _id=”19″ ][cs_element_layout_row _id=”20″ ][cs_element_layout_column _id=”21″ ][cs_element_headline _id=”22″ ][cs_content_seo]Why choose a Codasip RISC‑V Processor?\n\n[/cs_content_seo][/cs_element_layout_column][/cs_element_layout_row][cs_element_layout_grid _id=”23″ ][cs_element_layout_cell _id=”24″ ][cs_element_creative_cta _id=”25″ ][cs_content_seo]Rich portfolioto fit your needs\n\nSelect from our wide selection of cores. Whatever domain or application area, we’ve got you covered.\n\nCheck out the portfolio\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”26″ ][cs_element_creative_cta _id=”27″ ][cs_content_seo]Precise resultswithout compromise\n\nCodasip cores are fully and easily customizable with Codasip Studio. Get a tailored core with the optimal features and PPA!\n\nLearn how we make customization easy\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”28″ ][cs_element_creative_cta _id=”29″ ][cs_content_seo]Advanced IDEincluded\n\nGet the handy CodeSpace IDE with any Codasip RISC-V Processor core to develop software for it. Full version is included!\n\nCheck out CodeSpace\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”30″ ][cs_element_creative_cta _id=”31″ ][cs_content_seo]Longevity, portability,compliance\n\nDon’t be limited by proprietorship thanks to cores built on open standards such as LLVM, UVM, and SystemC.\n\nDownload full brochure to read more\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”32″ ][cs_element_creative_cta _id=”33″ ][cs_content_seo]Protection from extra costs& vendor lock-in\n\nTake advantage of the free and open RISC-V ISA and its solid ecosystem supported by industry leaders.\n\nLearn about benefits of RISC-V\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”34″ ][cs_element_layout_grid _id=”35″ ][cs_element_layout_cell _id=”36″ ][cs_element_button _id=”37″ ][cs_content_seo]Download flyer\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”38″ ][cs_element_button _id=”39″ ][cs_content_seo]Get full brochure\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”40″ ][cs_element_button _id=”41″ ][cs_content_seo]Get e-book\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”42″ ][cs_element_layout_grid _id=”43″ ][cs_element_layout_cell _id=”44″ ][cs_element_headline _id=”45″ ][cs_content_seo]Codasip RISC‑V Processors at a Glance\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”46″ ][cs_element_text _id=”47″ ][cs_content_seo]Codasip offers three processor families:

Small and energy-efficient Low Power Embedded cores
More powerful High Performance Embedded cores
Most advanced Application cores able to run Linux

In each of the families, you can choose from a number of series based on the microarchitecture complexity.
All the cores are fully customizable and adaptable to the unique needs of your project.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”48″ ][cs_element_image _id=”49″ ][/cs_element_layout_cell][cs_element_layout_cell _id=”50″ ][cs_element_button _id=”51″ ][cs_content_seo]How to customize a Codasip core?\n\n[/cs_content_seo][cs_element_button _id=”52″ ][cs_content_seo]Read case study on customization\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”53″ ][cs_element_layout_row _id=”54″ ][cs_element_layout_column _id=”55″ ][cs_element_headline _id=”56″ ][cs_content_seo]Choose your Codasip RISC‑V Processor\n\n[/cs_content_seo][/cs_element_layout_column][/cs_element_layout_row][cs_element_layout_grid _id=”57″ ][cs_element_layout_cell _id=”58″ ][cs_element_headline _id=”59″ ][cs_content_seo]F = Floating Point Unit, P = RISC-V P Packed SIMD Extension, MP = Multiprocessing *Not recommended for new designs.\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_row _id=”60″ ][cs_element_layout_column _id=”61″ ][cs_element_text _id=”62″ ][cs_content_seo]All Cores\n\n[/cs_content_seo][cs_element_text _id=”63″ ][cs_content_seo]Standard RISC-V debug
JTAG (4pin/2pin)
Compressed instructions
AMBA buses
\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”64″ ][cs_element_text _id=”65″ ][cs_content_seo]Low Power Embedded\n\n[/cs_content_seo][cs_element_text _id=”66″ ][cs_content_seo]32-bit
Up to 128 interrupts
\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”67″ ][cs_element_text _id=”68″ ][cs_content_seo]High Performance Embedded\n\n[/cs_content_seo][cs_element_text _id=”69″ ][cs_content_seo]64-bit
Up to 256 interrupts
\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”70″ ][cs_element_text _id=”71″ ][cs_content_seo]Application\n\n[/cs_content_seo][cs_element_text _id=”72″ ][cs_content_seo]64-bit
Floating point unit
Linux support:

RV64GC ISA
Atomic instructions
Supervisor mode
MMU

Multicore options
Dual-issue options
\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”73″ ][cs_element_image _id=”74″ ][cs_element_text _id=”75″ ][cs_content_seo]7-stage pipeline
IMC instruction set
32 registers
Branch predictor
Parallel multiplier
\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”76″ ][/cs_element_layout_column][cs_element_layout_column _id=”77″ ][/cs_element_layout_column][cs_element_layout_column _id=”78″ ][cs_element_text _id=”79″ ][cs_content_seo]Codasip A70
Codasip A70P
Codasip A70-MP
Codasip A70P-MP\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”80″ ][cs_element_image _id=”81″ ][cs_element_text _id=”82″ ][cs_content_seo]5-stage pipeline
IMC instruction set
32 registers
Branch predictor
Parallel multiplier
\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”83″ ][cs_element_text _id=”84″ ][cs_content_seo]Codasip L50
Codasip L50F\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”85″ ][cs_element_text _id=”86″ ][cs_content_seo]Codasip H50
Codasip H50F\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”87″ ][/cs_element_layout_column][cs_element_layout_column _id=”88″ ][cs_element_image _id=”89″ ][cs_element_text _id=”90″ ][cs_content_seo]3-stage pipeline
IMC instruction set
32 registers
Parallel multiplier
\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”91″ ][cs_element_text _id=”92″ ][cs_content_seo]Codasip L31
Codasip L31F\n\n[/cs_content_seo][cs_element_text _id=”93″ ][cs_content_seo]Codasip L30*
Codasip L30F*\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”94″ ][/cs_element_layout_column][cs_element_layout_column _id=”95″ ][/cs_element_layout_column][cs_element_layout_column _id=”96″ ][cs_element_image _id=”97″ ][cs_element_text _id=”98″ ][cs_content_seo]3-stage pipeline
EMC instruction set
16 registers
Sequential multiplier
\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”99″ ][cs_element_text _id=”100″ ][cs_content_seo]Codasip L11\n\n[/cs_content_seo][cs_element_text _id=”101″ ][cs_content_seo]Codasip L10*\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”102″ ][/cs_element_layout_column][cs_element_layout_column _id=”103″ ][/cs_element_layout_column][/cs_element_layout_row][/cs_element_section][cs_element_section _id=”104″ ][cs_element_layout_row _id=”105″ ][cs_element_layout_column _id=”106″ ][cs_element_headline _id=”107″ ][cs_content_seo]Choose your Codasip RISC-V Processor\n\n[/cs_content_seo][/cs_element_layout_column][/cs_element_layout_row][cs_element_layout_row _id=”108″ ][cs_element_layout_column _id=”109″ ][cs_element_headline _id=”110″ ][cs_content_seo]Click the image to enlarge\n\n[/cs_content_seo][cs_element_image _id=”111″ ][/cs_element_layout_column][/cs_element_layout_row][/cs_element_section][cs_element_section _id=”112″ ][cs_element_layout_grid _id=”113″ ][cs_element_layout_cell _id=”114″ ][cs_element_headline _id=”115″ ][cs_content_seo]FPGA Evaluation Platform\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”116″ ][cs_element_text _id=”117″ ][cs_content_seo]If you would like to evaluate a single Codasip RISC-V core, you can use Codasip’s FPGA evaluation platform. Codasip will supply you with an eval kit consisting of an FPGA bitstream, SDK and the CodeSpace IDE, along with a step-by-step quick start guide. You should be up and running with your first C program in 15 minutes.
Please note that obtaining the package is subject to signing an Evaluation Agreement. You are welcome to contact us for more details.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”118″ ][cs_element_button _id=”119″ ][cs_content_seo]Download flyer\n\n[/cs_content_seo][cs_element_button _id=”120″ ][cs_content_seo]Get a quote/eval\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_row _id=”121″ ][cs_element_layout_column _id=”122″ ][cs_element_tabs _modules=”124,125″ _id=”123″ ][/cs_element_tabs][/cs_element_layout_column][/cs_element_layout_row][/cs_element_section][cs_element_section _id=”126″ ][cs_element_layout_grid _id=”127″ ][cs_element_layout_cell _id=”128″ ][cs_element_headline _id=”129″ ][cs_content_seo]Read our articles\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_row _id=”130″ ][cs_element_layout_column _id=”131″ ][cs_element_layout_row_2 _id=”132″ ][cs_element_layout_column_2 _id=”133″ ][cs_element_layout_div _id=”134″ ][cs_element_layout_div_2 _id=”135″ ][cs_element_image _id=”136″ ][/cs_element_layout_div_2][cs_element_layout_grid _id=”137″ ][cs_element_layout_cell _id=”138″ ][cs_element_text _id=”139″ ][cs_content_seo]{{dc:post:publish_date format=’d M, y’}}\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”140″ ][cs_element_text _id=”141″ ][cs_content_seo]{{dc:term:name}}\n\n[/cs_content_seo][cs_element_text _id=”142″ ][cs_content_seo]by {{dc:author:display_name}}\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”143″ ][cs_element_headline _id=”144″ ][cs_content_seo]{{dc:post:title}}\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_layout_div][/cs_element_layout_column_2][/cs_element_layout_row_2][/cs_element_layout_column][/cs_element_layout_row][/cs_element_section][cs_element_section _id=”145″ ][cs_element_layout_grid _id=”146″ ][cs_element_layout_cell _id=”147″ ][cs_element_headline _id=”148″ ][cs_content_seo]I want a Codasip RISC‑V Processor\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”149″ ][contact-form-7 id=”534″ title=”Product: Codasip Processors”][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][/cs_content]