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Codasip SweRV内核支持包

[cs_content][cs_element_section _id=”1″ ][cs_element_layout_grid _id=”2″ ][cs_element_layout_cell _id=”3″ ][cs_element_headline _id=”4″ ][cs_content_seo]Codasip SweRV Core Support Package\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”5″ ][cs_element_layout_grid _id=”6″ ][cs_element_layout_cell _id=”7″ ][cs_element_headline _id=”8″ ][cs_content_seo]Codasip SweRV Core Support Package\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”9″ ][cs_element_text _id=”10″ ][cs_content_seo]The SweRV Core Support Package provided exclusively by Codasip presents an easy, safe and cost-effective way to develop a SoC based on a SweRV Core. The SweRV core family offers a selection of free RISC-V® processor cores developed by Western Digital®. The package contains a complete set of components, set-up flows, and professional technical support to enable SweRV core deployment.
The package contains the Free version, hosted by the CHIPSAlliance GitHub repository.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”11″ ][cs_element_button _id=”12″ ][cs_content_seo]Discover the benefits\n\n[/cs_content_seo][cs_element_button _id=”13″ ][cs_content_seo]Discover SweRV Cores\n\n[/cs_content_seo][cs_element_button _id=”14″ ][cs_content_seo]Discover the Package\n\n[/cs_content_seo][cs_element_button _id=”15″ ][cs_content_seo]Get the Free version\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_row _id=”16″ ][cs_element_layout_column _id=”17″ ][cs_element_testimonial _id=”18″ ][cs_content_seo]Choosing the open RISC-V architecture protects your investment in system software, thus minimizing risk; no longer is it necessary to depend on closed ecosystems or a single vendor. With Codasip SweRV Core Support Package, adopting an open core has never been easier!\n\n[/cs_content_seo][/cs_element_layout_column][/cs_element_layout_row][/cs_element_section][cs_element_section _id=”19″ ][cs_element_layout_row _id=”20″ ][cs_element_layout_column _id=”21″ ][cs_element_headline _id=”22″ ][cs_content_seo]Why choose a SweRV Core and the Support Package?\n\n[/cs_content_seo][/cs_element_layout_column][/cs_element_layout_row][cs_element_layout_grid _id=”23″ ][cs_element_layout_cell _id=”24″ ][cs_element_creative_cta _id=”25″ ][cs_content_seo]Unrivaled cost effectivity\n\nWith the free RTL and effort-saving package, implement a SweRV-based chip at a fraction of the cost of competing technologies.\n\nCheck out\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”26″ ][cs_element_creative_cta _id=”27″ ][cs_content_seo]Backed by strong players\n\nRely on cores developed for use in their own products by Western Digital, the global provider of data storage solutions.\n\nLearn how\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”28″ ][cs_element_creative_cta _id=”29″ ][cs_content_seo]Safe choice with expert support\n\nEnjoy ready-to-use EDA flows and software toolchain. When stuck, get guaranteed expert help. No risk, just peace of mind!\n\nCheck out\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”30″ ][cs_element_layout_row _id=”31″ ][cs_element_layout_column _id=”32″ ][cs_element_layout_grid _id=”33″ ][cs_element_layout_cell _id=”34″ ][cs_element_video _id=”35″ ][/cs_element_layout_cell][cs_element_layout_cell _id=”36″ ][cs_element_text _id=”37″ ][cs_content_seo]Codasip SweRV Core Support Package:
Video Introduction\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_layout_column][/cs_element_layout_row][/cs_element_section][cs_element_section _id=”38″ ][cs_element_layout_row _id=”39″ ][cs_element_layout_column _id=”40″ ][cs_element_headline _id=”41″ ][cs_content_seo]The SweRV Cores\n\n[/cs_content_seo][cs_element_text _id=”42″ ][cs_content_seo]The SweRV Cores are RISC-V processor cores developed by Western Digital for use in their upcoming products. The RTL source of the cores is available free of charge from the CHIPSAlliance repository on GitHub, or as a part of a comprehensive, ready-to-go Support Package from Codasip.
There are currently three SweRV Cores to choose from: EH1, the powerful, two-way superscalar core, EH2, even more powerful core based on EH1 with added dual threading, and finally EL2, the ultra low-power minimalist core.\n\n[/cs_content_seo][cs_element_button _id=”43″ ][cs_content_seo]More info from Western Digital\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”44″ ][cs_element_image _id=”45″ ][/cs_element_layout_column][/cs_element_layout_row][cs_element_layout_row _id=”46″ ][cs_element_layout_column _id=”47″ ][cs_element_tabs _modules=”49,50,51″ _id=”48″ ][/cs_element_tabs][cs_element_text _id=”52″ ][cs_content_seo]* Benchmark source: Western Digital, RISC-V Summit 2020/12. Further gain is usually possible with compiler optimizations.\n\n[/cs_content_seo][/cs_element_layout_column][/cs_element_layout_row][/cs_element_section][cs_element_section _id=”53″ ][cs_element_layout_row _id=”54″ ][cs_element_layout_column _id=”55″ ][cs_element_headline _id=”56″ ][cs_content_seo]SweRV Core Support Package\n\n[/cs_content_seo][/cs_element_layout_column][/cs_element_layout_row][cs_element_layout_row _id=”57″ ][cs_element_layout_column _id=”58″ ][cs_element_text _id=”59″ ][cs_content_seo]The SweRV Core Support Package makes it possible to implement a RISC-V-based SweRV Core avoiding the hidden costs associated with open source core deployment. The package covers everything needed to deploy the core, from comprehensive support for traditional 3rd party design flows to all the components necessary to design, implement, test, and write software for a SweRV-based system-on-chip.\n\n[/cs_content_seo][/cs_element_layout_column][cs_element_layout_column _id=”60″ ][cs_element_button _id=”61″ ][cs_content_seo]Get the Free version\n\n[/cs_content_seo][/cs_element_layout_column][/cs_element_layout_row][cs_element_layout_row _id=”62″ ][cs_element_layout_column _id=”63″ ][cs_element_headline _id=”64″ ][cs_content_seo]What’s Included\n\n[/cs_content_seo][cs_element_text _id=”65″ ][cs_content_seo]Easy-to-deploy IDE, with open-source EDA tools and scripts for commercial tools set up and ready to use
RTL designs: Stable versions of the selected SweRV Core and an example SoC design (SweRVOlf)
Software Development Tools: Compiler toolchain (GNU) and on-chip debugger (OpenOCD)
Hardware Development Tools: Open-source simulators (Verilator, Whisper ISS) and support for leading commercial simulators, linters, synthesizers
Comprehensive documentation, samples, libraries
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