Codasip SweRV Core Support Package

Codasip SweRV Core Support Package

The SweRV Core Support Package provided exclusively by Codasip presents an easy, safe and cost-effective way to develop a SoC based on a SweRV Core. The SweRV core family offers a selection of free RISC-V® processor cores developed by Western Digital®. The package contains a complete set of components, set-up flows, and professional technical support to enable SweRV core deployment.

The package contains the Free version, hosted by the CHIPSAlliance GitHub repository.

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Discover SweRV Cores
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Choosing the open RISC-V architecture protects your investment in system software, thus minimizing risk; no longer is it necessary to depend on closed ecosystems or a single vendor. With Codasip SweRV Core Support Package, adopting an open core has never been easier!

Why choose a SweRV Core and the Support Package?

Unrivaled cost effectivityWith the free RTL and effort-saving package, implement a SweRV-based chip at a fraction of the cost of competing technologies.
Backed by strong playersRely on cores developed for use in their own products by Western Digital, the global provider of data storage solutions.
Safe choice with expert supportEnjoy ready-to-use EDA flows and software toolchain. When stuck, get guaranteed expert help. No risk, just peace of mind!
Codasip SweRV Core Support Package:

Video Introduction

The SweRV Cores

The SweRV Cores are RISC-V processor cores developed by Western Digital for use in their upcoming products. The RTL source of the cores is available free of charge from the CHIPSAlliance repository on GitHub, or as a part of a comprehensive, ready-to-go Support Package from Codasip.

There are currently three SweRV Cores to choose from: EH1, the powerful, two-way superscalar core, EH2, even more powerful core based on EH1 with added dual threading, and finally EL2, the ultra low-power minimalist core.

More info from Western Digital
SweRV cores complex block diagram

The SweRV Core EH1 is an advanced high-performance core with small footprint, suitable for embedded devices supporting data-intensive applications such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems.

  • Architecture: RV32IMC
  • Pipeline: 9-stage dual issue
  • Threads: Single
  • Size @ TSMC: .11mm @ 28nm
  • Performance: 5.7 CoreMark/MHz*
* Benchmark source: Western Digital, RISC-V Summit 2020/12. Further gain is usually possible with compiler optimizations.

SweRV Core Support Package

The SweRV Core Support Package makes it possible to implement a RISC-V-based SweRV Core avoiding the hidden costs associated with open source core deployment. The package covers everything needed to deploy the core, from comprehensive support for traditional 3rd party design flows to all the components necessary to design, implement, test, and write software for a SweRV-based system-on-chip.
Get the Free version

What's Included

  • Easy-to-deploy IDE, with open-source EDA tools and scripts for commercial tools set up and ready to use
  • RTL designs: Stable versions of the selected SweRV Core and an example SoC design (SweRVOlf)
  • Software Development Tools: Compiler toolchain (GNU) and on-chip debugger (OpenOCD)
  • Hardware Development Tools: Open-source simulators (Verilator, Whisper ISS) and support for leading commercial simulators, linters, synthesizers
  • Comprehensive documentation, samples, libraries