Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

领域专用处理器

[cs_content][cs_element_section _id=”1″ ][cs_element_layout_grid _id=”2″ ][cs_element_layout_cell _id=”3″ ][cs_element_text _id=”4″ ][cs_content_seo]Domain-Specific AcceleratorsOptimize Performance, Power & Area\n\n[/cs_content_seo][cs_element_text _id=”5″ ][cs_content_seo]Domain-specific accelerators help compensate for the breakdown of Moore’s law. They make it possible to continue improving processor performance without increasing power and area.\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”6″ ][cs_element_layout_grid _id=”7″ ][cs_element_layout_cell _id=”8″ ][cs_element_image _id=”9″ ][/cs_element_layout_cell][cs_element_layout_cell _id=”10″ ][cs_element_text _id=”11″ ][cs_content_seo]Processor Specialization
Creating Domain-Specific Accelerators\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”12″ ][cs_element_text _id=”13″ ][cs_content_seo]The breakdown of semiconductor scaling is driving the demand for domain-specific accelerators.
Such accelerators are specialized to varying degrees.
The advantage?
Greater specialization → greater area and energy efficiency!\n\n[/cs_content_seo][cs_element_button _id=”14″ ][cs_content_seo]Watch intro to Domain-Specific Accelerators\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”15″ ][cs_element_layout_grid _id=”16″ ][cs_element_layout_cell _id=”17″ ][cs_element_image _id=”18″ ][/cs_element_layout_cell][cs_element_layout_cell _id=”19″ ][cs_element_text _id=”20″ ][cs_content_seo]Domain-specific accelerators can vary in their degree of specialization: Very specialized cores with limited programmability are close to hardwired logic. Less specialized ones are closer to general-purpose cores.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”21″ ][cs_element_headline _id=”22″ ][cs_content_seo]How much specialization?\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”23″ ][cs_element_layout_grid _id=”24″ ][cs_element_layout_cell _id=”25″ ][cs_element_headline _id=”26″ ][cs_content_seo]What is the Challenge?\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”27″ ][cs_element_text _id=”28″ ][cs_content_seo]Many accelerator designs are going to be created to compensate for semiconductor scaling. It is going to be very important that they are designed and verified in an efficient way.
There are two complementary ways to tackle this challenge:

\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_grid _id=”29″ ][cs_element_layout_cell _id=”30″ ][cs_element_text _id=”31″ ][cs_content_seo]1\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”32″ ][cs_element_text _id=”33″ ][cs_content_seo]Accelerate the design cycle by using design automation tools\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_grid _id=”34″ ][cs_element_layout_cell _id=”35″ ][cs_element_text _id=”36″ ][cs_content_seo]Codasip Studio provides a suite of tools for automating the design of programmable cores using the CodAL architecture description language.
CodAL can be used to create both an instruction accurate (IA) description of a processor and cycle accurate (CA) or microarchitectural description. Codasip Studio then automatically generates the SDK and HDK from the CodAL description.\n\n[/cs_content_seo][cs_element_line _id=”37″ ][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_grid _id=”38″ ][cs_element_layout_cell _id=”39″ ][cs_element_text _id=”40″ ][cs_content_seo]2\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”41″ ][cs_element_text _id=”42″ ][cs_content_seo]Reduce the design time by customizing an existing processor core\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_grid _id=”43″ ][cs_element_layout_cell _id=”44″ ][cs_element_text _id=”45″ ][cs_content_seo]If the wordlengths and ISA of RISC-V are suitable for creating an accelerator by customization, then Codasip RISC-V Processors are an excellent starting point.
The cores can be licensed in CodAL source code, and your design team can create custom extensions to optimize the core for your application. Codasip Studio then provides automation to help you with rigorously verifying the modified core.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”46″ ][cs_element_button _id=”47″ ][cs_content_seo]Discover Codasip RISC-V Processors\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”48″ ][cs_element_button _id=”49″ ][cs_content_seo]Discover the Codasip Studio toolset\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”50″ ][cs_element_layout_grid _id=”51″ ][cs_element_layout_cell _id=”52″ ][cs_element_headline _id=”53″ ][cs_content_seo]Contact Us\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”54″ ][contact-form-7 id=”8420″ title=”GENERAL”][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][/cs_content]