Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

创建全新处理器

[cs_content][cs_element_section _id=”1″ ][cs_element_layout_grid _id=”2″ ][cs_element_layout_cell _id=”3″ ][cs_element_text _id=”4″ ][cs_content_seo]New Processor Creation
Design a Novel Core from Scratch\n\n[/cs_content_seo][cs_element_text _id=”5″ ][cs_content_seo]Need something very special and unique? Customization of an existing core won’t do? Design the instruction set and microarchitecture yourself. It can be easier than you think.\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”6″ ][cs_element_layout_grid _id=”7″ ][cs_element_layout_cell _id=”8″ ][cs_element_image _id=”9″ ][/cs_element_layout_cell][cs_element_layout_cell _id=”10″ ][cs_element_text _id=”11″ ][cs_content_seo]Processor Creation
When is it time to start from scratch?\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”12″ ][cs_element_text _id=”13″ ][cs_content_seo]If you have requirements that cannot be met by an off-the-shelf processor IP core even after customization, then you need to design the instruction set and microarchitecture from scratch. If you want to work with 32-bit or 64-bit operands, then the corresponding RISC-V base integer ISA might be a good starting point. However, if you need for example 8- or 16-bit operands, you will need something quite different.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”14″ ][cs_element_button _id=”15″ ][cs_content_seo]What do I need next?\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_grid _id=”16″ ][cs_element_layout_cell _id=”17″ ][cs_element_image _id=”18″ ][/cs_element_layout_cell][cs_element_layout_cell _id=”19″ ][cs_element_text _id=”20″ ][cs_content_seo]Basic requirements
Instruction set and microarchitecture\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”21″ ][cs_element_text _id=”22″ ][cs_content_seo]Whether you want to create a RISC-V, VLIW, DSP or other processor, you will need to define and refine your instruction set and then go on to developing your microarchitecture. To optimize your instruction set, you need to analyze representative software that you intend to run in order to be sure that your ISA ends up delivering the performance that you need.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”23″ ][cs_element_button _id=”24″ ][cs_content_seo]How to do that easily?\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”25″ ][cs_element_layout_grid _id=”26″ ][cs_element_layout_cell _id=”27″ ][cs_element_headline _id=”28″ ][cs_content_seo]Codasip Studio
The smarter & faster way to design\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”29″ ][cs_element_button _id=”30″ ][cs_content_seo]Discover Codasip Studio\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”31″ ][cs_element_text _id=”32″ ][cs_content_seo]Codasip Studio enables you to develop your ISA with the SDK and HDK in the loop:

\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_grid _id=”33″ ][cs_element_layout_cell _id=”34″ ][cs_element_text _id=”35″ ][cs_content_seo]1\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”36″ ][cs_element_text _id=”37″ ][cs_content_seo]Define your architectural resources and ISA (whether based on RISC-V or from scratch) using the CodAL language.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”38″ ][cs_element_text _id=”39″ ][cs_content_seo]2\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”40″ ][cs_element_text _id=”41″ ][cs_content_seo]Generate your SDK.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”42″ ][cs_element_text _id=”43″ ][cs_content_seo]3\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”44″ ][cs_element_text _id=”45″ ][cs_content_seo]Compile, run, and profile your application software. Codasip Studio supports HW/SW co-simulation, so you can step through your software and observe what CodAL code is being exercised. \n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”46″ ][cs_element_text _id=”47″ ][cs_content_seo]4\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”48″ ][cs_element_text _id=”49″ ][cs_content_seo]After analyzing the results, you can update the ISA and go through the loop again until you are happy with the instruction accurate (IA) description.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”50″ ][cs_element_text _id=”51″ ][cs_content_seo]5\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”52″ ][cs_element_text _id=”53″ ][cs_content_seo]With a stable IA, you can go on to define your microarchitecture in CodAL.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”54″ ][cs_element_text _id=”55″ ][cs_content_seo]6\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”56″ ][cs_element_text _id=”57″ ][cs_content_seo]Generate your HDK.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”58″ ][cs_element_text _id=”59″ ][cs_content_seo]7\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”60″ ][cs_element_text _id=”61″ ][cs_content_seo]Run software using a cycle accurate (CA) simulator, or an RTL simulator or an FPGA prototype. Based on how the profiling goes, you may want to fine-tune the microarchitecture. You can generate the RTL, testbench, and UVM environment from the CodAL CA description as part of the HDK.\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_grid _id=”62″ ][cs_element_layout_cell _id=”63″ ][cs_element_image _id=”64″ ][/cs_element_layout_cell][cs_element_layout_cell _id=”65″ ][cs_element_text _id=”66″ ][cs_content_seo]Rigorous verification made easy\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”67″ ][cs_element_text _id=”68″ ][cs_content_seo]Finally, you will need to verify that your generated RTL matches the golden IA reference. Processor verification is probably the most important part of the design cycle and Codasip Studio ensures high productivity. Not only is the UVM environment generated with functional coverpoints, but you can automatically generate random assembler programs to ensure high code coverage.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”69″ ][cs_element_button _id=”70″ ][cs_content_seo]I want Codasip Studio!\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”71″ ][cs_element_layout_grid _id=”72″ ][cs_element_layout_cell _id=”73″ ][cs_element_headline _id=”74″ ][cs_content_seo]Contact Us\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”75″ ][contact-form-7 id=”8420″ title=”GENERAL”][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][/cs_content]