Welcome to Codasip

New Processor Creation

Design a Novel Core from Scratch

Need something very special and unique? Customization of an existing core won't do? Design the instruction set and microarchitecture yourself. It can be easier than you think.


Processor Creation

When is it time to start from scratch?

If you have requirements that cannot be met by an off-the-shelf processor IP core even after customization, then you need to design the instruction set and microarchitecture from scratch. If you want to work with 32-bit or 64-bit operands, then the corresponding RISC-V base integer ISA might be a good starting point. However, if you need for example 8- or 16-bit operands, you will need something quite different.

Basic requirements

Instruction set and microarchitecture

Whether you want to create a RISC-V, VLIW, DSP or other processor, you will need to define and refine your instruction set and then go on to developing your microarchitecture. To optimize your instruction set, you need to analyze representative software that you intend to run in order to be sure that your ISA ends up delivering the performance that you need.

Codasip Studio

The smarter & faster way to design

Codasip Studio enables you to develop your ISA with the SDK and HDK in the loop:


    Define your architectural resources and ISA (whether based on RISC-V or from scratch) using the CodAL language.


    Generate your SDK.


    Compile, run, and profile your application software. Codasip Studio supports HW/SW co-simulation, so you can step through your software and observe what CodAL code is being exercised.


    After analyzing the results, you can update the ISA and go through the loop again until you are happy with the instruction accurate (IA) description.


    With a stable IA, you can go on to define your microarchitecture in CodAL.


    Generate your HDK.


    Run software using a cycle accurate (CA) simulator, or an RTL simulator or an FPGA prototype. Based on how the profiling goes, you may want to fine-tune the microarchitecture. You can generate the RTL, testbench, and UVM environment from the CodAL CA description as part of the HDK.

    Rigorous verification made easy

    Finally, you will need to verify that your generated RTL matches the golden IA reference. Processor verification is probably the most important part of the design cycle and Codasip Studio ensures high productivity. Not only is the UVM environment generated with functional coverpoints, but you can automatically generate random assembler programs to ensure high code coverage.

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