The SweRV Core™ Support Package from Codasip provides everything needed to deploy a SweRV-based system-on-chip. The package contains a complete set of components, useful tools, and professional technical support.
The SweRV Core
The SweRV Cores EH1, EH2 and EL2 are a family of RISC-V cores developed by Western Digital for use in their upcoming products. Hosted and curated by the CHIPS Alliance, all the core designs are open for the RISC-V community to utilize and contribute to.
The RTL source is available free of charge on GitHub, or as a part of a comprehensive, ready-to-go Support Package from Codasip.
The SweRV Core™ EH1 is an advanced high-performance core with small footprint, suitable for embedded devices supporting data-intensive applications such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems.
EH2 was built off of the EH1 and it adds dual threaded capability for additional performance.
EL2 is a small, ultra-low-power core with moderate performance, optimized for applications such as state-machine sequencers and waveform generators. It was designed to replace state machines and other logic functions in SoCs.
SweRV Core EH1:
- Architecture: 32-bit, dual superscalar, 9-stage pipeline
- Performance: Up to 4.95 CoreMark/MHz (further gain possible with compiler optimizations)
- Clock speed: Up to 1.8 GHz
- Technology: TSMC 28nm CMOS
- Bus support: AXI, AHB-lite
- Programmable Interrupt Controller
- RISC-V debug support
SweRV Core EH2:
- Performance: Up to 6.3 CoreMark/MHz
The Support Package
The SweRV Core Support Package makes it possible to implement a RISC-V-based SweRV Core at a fraction of the cost of competing technologies. The package covers everything needed to deploy the core, from comprehensive support for traditional 3rd party design flows to all the components necessary to design, implement, test, and write software for a SweRV-based system-on-chip.
Integrated Development Environment
Easy-to-deploy IDE, with open-source EDA tools and scripts for commercial tools set up and ready to use
Stable versions of the selected SweRV Core and an example SoC design (SweRVOlf)
Software Development Tools
Compiler toolchain (GNU) and on-chip debugger (OpenOCD)
Hardware Development Tools
Open-source simulators (Verilator, Whisper ISS) and support for leading commercial simulators, linters, synthesizers
Docs and Examples
Comprehensive documentation, samples, libraries
Expert support via online forums, e-mail, phone, and on-site
Customization, optimization, and full verification of your core as on-request services
“Choosing the open RISC-V architecture protects your investment in system software, thus minimizing risk; no longer is it necessary to depend on closed ecosystems or a single vendor. With Codasip SweRV Core Support Package, adopting an open core has never been easier!”