SweRV EH1 Support Package
The SweRV Support Package (SSP) from Codasip provides everything needed to deploy a SweRV-based system-on-chip. The package contains a complete set of components, useful tools, and professional technical support.
“Choosing the open RISC-V architecture protects your investment in system software, thus minimizing risk; no longer is it necessary to depend on closed ecosystems or a single vendor. With SweRV and Codasip SSP, adopting an open core has never been easier!”
The SweRV Core™ EH1 is an advanced high-performance core with small footprint, suitable for embedded devices supporting data-intensive applications such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems. The core is going to be used in Western Digital products in the coming years. The design is open for the RISC-V community to utilize and contribute to.
- Architecture: 32-bit, dual superscalar, 9-stage pipeline
- Performance: Up to 4.95 CoreMark/MHz (based on simulations; further gain possible with compiler optimizations)
- Clock speed: Up to 1.8 GHz
- Technology: TSMC 28nm CMOS
- Bus support: AXI, AHB-lite
- Programmable Interrupt Controller
- RISC-V debug support
The Support Package
The SweRV Support Package (SSP) by Codasip makes it possible to implement the RISC-V SweRV core at a fraction of the cost of competing technologies. SSP covers everything needed to deploy the core, from comprehensive support for traditional 3rd party design flows to all the components necessary to design, implement, test, and write software for a SweRV-based system-on-chip.
Reference scripts for Synopsys Design Compiler and VCS, Cadence Genus, Mentor Questa
Example verification testbenches in SystemVerilog
Support for FPGA emulation flows
Compiler toolchain and IDE
Expert online technical support
Comprehensive online documentation