Below you'll find a list of all posts that have been tagged as “CHIPSAlliance”
In the last three months, Codasip’s RISC-V processor offering has expanded considerably. For some years, Codasip has supplied Bk3 and Bk5 RISC-V cores aimed at low- to medium-complexity embedded applications. But recently four additional cores have joined the Codasip RISC-V offering.
The Moore’s law has had remarkably long validity of almost half a century. Today, however, it is ceasing to apply, opening new pressing questions such as: How to make up for the fact that chip size cannot be effectively reduced any more? What is the new way to improve performance? Roddy’s blogpost digs into one of the most promising answers: Core customization. Read on!
Codasip announces the availability of support to the two new SweRV cores, EH1 and EH2. Both are now available, along with all necessary tools and workflows, within Codasip’s exclusive SweRV Support Package.
