Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

Vidtoo Technology Licenses Codasip’s Bk3 RISC‑V Processor for High‑Performance Computing SoC


December 17, 2018

Munich, Germany – December 17th 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, announced today that Vidtoo Technology, a leader in semiconductor products for machine learning and high-performance computing, has selected Codasip’s Bk3 processor for future HPC chips.

Vidtoo Technology, based in Hangzhou, China, focuses on high-bandwidth, high-performance, high-connectivity, artificial intelligence platforms and inference engines for data centers as well as 3D video processing technologies for industrial IoT applications and SR (Simulated Reality)/MR applications with on-chip decision making capabilities.

“We are pleased to announce our selection of Codasip’s Bk3 processor for our next HPC products. After careful consideration, we determined that Codasip offered the best combination of performance, value and design expansion ability. Those traits, plus best-in-class support and the broad ecosystem that the open RISC-V ISA brings, gave us confidence that Codasip was the right choice,” stated Thomas Hu, CEO of Vidtoo Technologies. “We look forward to a long and successful partnership with Codasip when we strive to provide customers with the optimal design across our product families.”

The Codasip Bk3 processor, based on the RISC-V open instruction set architecture (ISA) definition, features a single 3-stage in-order execution processor pipeline, and offers optional caches, IEEE 1149.1 debug, and industry standard bus interfaces. Further, the Bk3 – like all Codasip RISC-V implementations – is fully configurable and extensible, offering great advantage over traditional, fixed-configuration processor IP cores.

We are delighted that Vidtoo Technology has chosen Codasip to be its provider of RISC-V processor IP,” added Chris Jones, Codasip’s Vice President of Marketing. “Vidtoo is a rising star in the semiconductor industry with an impressive product portfolio that includes cutting-edge machine-learning devices. They have wide-ranging processing needs, and Codasip technology gives them a proven family of processor solutions complete with a comprehensive high-performance software toolchain.”

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information, visit www.riscv.org.

Kava

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Mythic Chooses Codasip to Deliver RISC-V Computing in their Revolutionary Neural Network Platform


December 10, 2018

Campbell, California – December 10th 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, announced today that Mythic, a leader in artificial intelligence (AI) computing technology, has selected Codasip’s configurable Bk3 processor and Codasip Studio for future neural networking chips.

Mythic, based in Redwood City, California, and Austin, Texas, will deliver powerful, life-enhancing AI solutions that customers can push into anything, from fitness bands and hearing aids to self-driving cars and security cameras. The solutions are developed on a unique approach to neural network processing. The Mythic Intelligence Processing Unit (IPU), which performs the inference step of deep neural networks inside the same flash memory array which stores the neural network’s weights, delivers huge advantages in performance, cost, and power consumption versus alternative solutions.

“We chose Codasip’s Bk3 RISC-V processor and Codasip Studio for our PCIe-attached IPU deep learning accelerator because it gave us the flexibility to create a truly unique processor that was specific to our needs, while maintaining compliance to the RISC-V standard,” stated Ty Garibay, VP of Hardware Engineering at Mythic. “While we have the expertise to build our own RISC-V processor, we determined that Codasip Studio, with its automatic generation of both verified hardware and fully compatible software toolchain, was a more efficient approach and allowed us to focus on other critical areas of the product development.”

The Codasip Bk3 processor, based on the RISC-V open instruction set architecture (ISA) definition, features a single 3-stage in-order execution processor pipeline and offers optional caches, IEEE 1149.1 debug, branch prediction, and industry standard bus interfaces. Further, the Bk3 – like all Codasip RISC-V implementations – is fully configurable and extensible, offering great advantage over traditional, fixed-configuration processor IP cores.

With Codasip Studio, designers can begin with a high-level description of a RISC-V micro-architectural implementation defined and delivered by Codasip, and then describe their desired architectural and ISA modifications in the CodAL architecture description language, and then automatically synthesize the design’s RTL, testbench, virtual platform models and processor SDK (C/C++ compiler, debugger, profiler, and other parts).  Time that would otherwise be required to maintain a complete SDK and implementation is significantly reduced thanks to the methodology that uses an Instruction Accurate (IA) processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.

We welcome Mythic to the growing roster of customers that are partnering with Codasip to deliver innovative products based on the RISC-V architecture,” stated Chris Jones, Codasip’s Vice President of Marketing. “RISC-V is ideal for machine learning applications, and Mythic will deliver revolutionary products that employ highly optimized Codasip RISC-V cores.”

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

About Mythic

Mythic is accelerating AI that works for everyone. Today, it is difficult, time-consuming and expensive to build and deploy reliable AI. By offering mixed-signal chips with revolutionary power, cost, and performance capabilities, along with easy-to-use software tools, Mythic is removing those limitations and empowering every AI developer. Mythic’s focus is simple: to enable the next great wave of AI innovation.

Mythic is supported by leading venture capital investors including Softbank, DFJ, Lux, and Data Collective. The company has offices in Austin, TX, and Redwood City, CA.  For more information about Mythic, visit www.mythic-ai.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information, visit www.riscv.org.

Kava

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Codasip Releases Studio 8, a Breakthrough in RISC-V Automation, and the Bk7 RISC-V Processor Core for Real-Time Computing Applications


December 6, 2018

Munich, Germany – December 6th, 2018 – CodasipGmbH, the leading supplier of RISC-V® embedded processor IP, announced today the latest version of Studio, a suite of tools optimized for the development and verification of RISC-V processors, and the Bk7 processor, the first Codasip RISC-V core optimized for Linux and real-time performance.

“As the RISC-V ISA specification evolves and adds an ever-increasing number of optional architecture extensions, a processor design methodology that allows for both rapid architectural exploration and simplified creation of easily implementable RTL becomes essential,” stated Chris Jones, Vice President of Marketing at Codasip. “What is needed is a high-level processor description language optimized for RISC-V, so Codasip has delivered Studio 8, a comprehensive tools suite for RISC-V processor development.”

With Studio, designers write a high-level description of a processor in CodAL, an architecture description language, and then automatically synthesize the design’s RTL, test bench, virtual platform models, and processor SDK (C/C++ compiler, debugger, profiler, etc.). Time that would otherwise be required to maintain a complete SDK and implementation is significantly reduced thanks to the methodology that uses an Instruction Accurate (IA) processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.

Codasip employs this silicon-proven methodology to create and deliver a broad portfolio of licensable RISC-V processor IP.  Through these product developments, Studio has evolved to make it more suitable for implementing and extending the instruction set of RISC-V cores. The 8th generation of Codasip Studio, just announced, adds significant new functionality and features, making it the most advanced and effective technology on the market for tailoring RISC-V processors to meet chip designers’ application-specific needs. Specifically, Studio 8 includes:

  • Support for LLVM debugger (LLDB) and OpenOCD,
  • LLVM 7.0,
  • Studio/CodeSpace IDEs based on Eclipse Oxygen along with more interactive consoles,
  • improved test suites and verification to better support user-defined RISC-V extensions.

Further, Codasip architects employed Studio to develop the Bk7 processor, the latest RISC-V micro-architecture in the Codasip portfolio.

A 64-bit machine featuring a balanced 7-stage pipeline with branch prediction, optional full MMU with virtual addressing support for operating systems such as Linux, and support for the popular RISC-V standard extensions as well as industry-standard external interfaces, the Bk7 is Codasip’s highest-performance processor to date and is ideal for system-on-chip designers who need the right balance of power and performance.  Also, the Bk7 is fully customizable so architects can easily add additional instructions, registers or interfaces. And as with each member of the Codasip Bk processor family, the Bk7 comes with the following deliverables:

  • Readable Verilog or VHDL RTL along with test benches and synthesis scripts,
  • SDK consisting of LLVM-based compiler, advanced profiling and debugging tools,
  • both cycle-accurate and fast instruction-accurate simulation tools.

Studio 8 and the Bk7 processor are generally available in the first quarter of 2019, with early access to selected customers immediately.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 with research and development located in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. Codasip is currently venture-backed by Credo Ventures, Ventech Capital, Shenzhen Capital, Paua Ventures, and Western Digital.

For more information about Codasip’s products and services, visit codasip.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open-standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information about RISC-V, visit www.riscv.org.[/cs_text][/cs_column][/cs_row][/cs_section][/cs_content]

Kava

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Dongwoon Anatech Licenses Codasip’s Bk3 RISC-V Processor for Motor Control ICs for Mobile Camera


April 23, 2018

Brno, Czech Republic, and Seoul, Korea – March 23rd 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, announced today that Dongwoon Anatech, a technology leader in analog and power ICs for mobile phones, has selected Codasip’s Bk3 processor and Studio design tool for its next generation family of motor control IC products.

Dongwoon Anatech, fabless analog semiconductor specialist, offers a wide range of analog products, including auto-focus driver IC for smartphones, AMOLED DC-DC converter, display power driver IC, and haptic driver IC.

We are pleased to announce our selection of Codasip’s Bk3 processor for our next motor control IC products. Analysis of the computational needs of our application showed that the RISC-V instruction set with custom DSP extensions was able to deliver the performance we require while keeping silicon area to a minimum,” stated Jin Park, CTO, Dongwoon Anatech. “The best-in-class Studio development tools enable us to profile our software and find an optimal set of instructions for our application.”

The Codasip Bk3 processor, based on the RISC-V open instruction set architecture (ISA) definition, features a single 3-stage in-order execution processor pipeline, and offers optional caches, IEEE 1149.1 debug, and industry standard bus interfaces. Further, the Bk3 – like all Codasip RISC-V implementations – is fully configurable and extensible, offering great advantage over traditional, fixed-configuration processor IP cores.

“We are delighted that Dongwoon Anatech has chosen Codasip to be its provider of RISC-V processor IP and associated design tools,” stated Chris Jones, Codasip’s Vice President of Marketing. “Dongwoon Anatech is a major player in providing analog integrated circuits for mobile phones, and thus needs efficient digital subsystems. Codasip technology provides them with a robust processor solution complete with a comprehensive high-performance software toolchain.”

About Dongwoon Anatech

Dongwoon Anatech is a ‘World class 300’ company that was established in 2006 and has grown over the past three decades to stand shoulder to shoulder with global fabless companies. Dongwoon Anatech has earned the world’s largest market share in the AF driver IC for smartphones, and has many customers including global clients such as Samsung, LG, Sony, and Huawei. In addition, Dongwoon Anatech plans to lead the world market by developing a variety of products including the haptic driver IC, DC-DC converter, display driver IC, and LED driver IC.

For more information, visit www.dwanatech.com.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information, visit www.riscv.org.

Kava

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Codasip Announces Bk5-64, a New 64-bit RISC-V Processor


November 28, 2017

Brno, Czech Republic – November 28th, 2017 – Codasip, the leading supplier of RISC-V® embedded processor IP, today announced that it has expanded its Berkelium processor portfolio to include the Bk5-64, its first implementation of the 64-bit RISC-V ISA.

Codasip now offers customers the broadest selection of RISC-V processors in the market, spanning from the ultra-low-power zero-stage Bk1 to the high-data-bandwidth, energy-efficient Bk5-64. All Berkelium processors are generated via the unique Codasip Studio customization tool, allowing for fast configuration and optimization of the cores.

With the rapid expansion of data-intensive applications such as storage and wireless networking, the market is asking for embedded processor solutions with the right balance of performance and energy efficiency that 64-bit computing requires,” stated Karel Masařík, founder and CEO of Codasip. “By introducing the Bk5-64, Codasip is addressing the need for affordable 64-bit embedded processors, complete with a state-of-the-art LLVM-based software development toolchain with advanced profiling.”

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

Said Rick O’Connor, Executive Director of the non-profit RISC-V Foundation, “Today’s announcement from Codasip shows continued growth of the RISC-V architecture and the industry’s need for a new open, free ISA. We look forward to seeing more developments from Codasip and others from the RISC-V ecosystem in the future.

The Berkelium Bk5-64 RISC-V processor is available later in Q4 of 2017.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

Kava

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Codasip Announces Latest RISC-V Processor


August 21, 2017

The Newest Codasip RISC-V Processor is Ideal for IoT Designs

Brno, Czech Republic – August 21st 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced the newest addition to their Berkelium (Bk) family of RISC-V processors. The Codasip Bk-1 processor is an FSM processor targeted at the Internet of Things (IoT) by offering ultra-low power, the lowest cost of all comparable embedded processors, and optimal performance/power efficiency.

Karel Masařík, CEO and founder of Codasip, stated: “This processor is perfect for IoT ASIC designers looking to move up from 8-bit processors to 32-bit processors. Like all members of the Codasip Bk family of processors, the Bk-1 is fully compliant with the RISC-V open standard, assuring customers that their embedded software is truly portable and their designs are not locked into a proprietary instruction set architecture (ISA) such as Arm.”

The Bk-1 processor was designed to provide impressive 32-bit performance, small code size, and minimal power, area, and cost. In its basic configuration, the Bk-1 starts at 9k gates while delivering a maximum clock frequency of up to 350 MHz in a 55nm process. The Bk-1 has an optional power management unit, JTAG debug controller, and bridges to the AMBA buses so it can be easily integrated into existing Arm designs.

Codasip provides their customers with high-level design tools that automatically profile the embedded SW and allow ASIC designers to tailor the Bk-1 processor exactly to its intended application. This unique ability to automatically modify the Codasip cores results in far better implementations compared to other processor IP vendors, and allows for the process to be easily completed in a day or two with the silicon proven Codasip Studio tool suite.

“Codasip’s new Bk-1 processor is another great milestone for the RISC-V ecosystem and shows ongoing market growth of its open and free architecture,” said Rick O’Connor, executive director of the non-profit RISC-V Foundation. “The Foundation will continue to support member organizations, such as Codasip, in bringing to market RISC-V-based processors that enable new designs and innovation.”

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of an open standard, such as the RISC-V ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V foundation (riscv.org) and a long-term supplier of LLVM and GNU based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. More information on Codasip’s products and services is available at codasip.com.

Press Contact

Codasip North America
Dan Ganousis
ganousis@codasip.com
+1 (303) 859-3048

Codasip EMEA
Roddy Urquhart
urquhart@codasip.com
+44 753 158 7023

Kava

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Does RISC-V mean Open Source Processors?


August 8, 2017

“RISC-V means open-source processors.” This is a statement that I have often heard this year – however, is it true or false? The answer is in this blog post.

Do open standards automatically mean open source?

Before answering the question “Does RISC-V Mean Open-Source Processors?”, let’s consider the broader issue of whether open standards automatically mean open source.

Open standards are widespread in technology. The communication protocols TCP/IP have been an open standard for decades. In wireless communication, Wi-Fi and Bluetooth are open standards with multiple versions.

In IC design, Verilog is an open standard maintained by the IEEE, and a widely used hardware description language. Verilog is used by a variety of commercial and open-source simulators. Incisive, Questa, and VCS are examples of well-known commercial simulators supporting Verilog, however Verilator & Cver are examples of open-source Verilog simulators. Generally, the commercial Verilog simulators are recognized for their high quality and performance.

RISC-V based processors can be either open-source or commercial

An open standard certainly does not rule out commercial products that use the standard. In the case of RISC-V, only the Instruction Set Architecture is standardized, leaving the microarchitecture and implementation to the processor developer. This gives ample opportunities for commercial processor cores. Commercial processor IP cores based on RISC-V will have their own features and value-add for example in microarchitecture and implementation.

Although there are open-source RISC-V processor cores including Zscale, Rocket, and BOOM from the University of California Berkeley, there are also commercial processor cores, such as Codasip RISC-V based processors.

Roddy Urquhart

Roddy Urquhart

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A Tale of Two Approaches to High-Performance IoT


June 21, 2017

EXTENSIBLE PROCESSORS VS ACCELERATORS – AND HOW RISC-V CHANGES THE DYNAMIC

If you were to ask any good designer today what is the best architecture for an SoC that needs to manage complex DSP or high bandwidth traffic demands – you will almost always find the recommendation of using one or more off-the-shelf processors, complimented by hardware accelerators to offload complex processing from the main cores. This solution should give the best power and performance outcome.

The accelerators are usually implemented as standalone RTL blocks connected to the main processor bus, and are optimized to be very efficient on the data types they work with. So on the surface they appear to be the logical choice to deliver optimal power and performance.

BUT, HOW DID THIS COMMON ARCHITECTURE COME ABOUT, AND IS IT ALWAYS THE BEST APPROACH?

The how it came about is an easy answer – it came about because when you have a fixed processor IP and an ISA that you cannot change, the use of accelerator IP to offload complex data manipulations is the only practical solution. So in a world dominated by ARM and MIPS, the use of hardware accelerators was the only option.

As they say, when all you have is a hammer, everything looks like a nail.

So the next part of the question is “Are accelerators the best solution?”

That is a much more nuanced discussion, and it is highly dependent on the specific application. What we can say is that for many of the cases when accelerators are used, they are sub optimal. In the narrow context of their own operation they save power (and processing time), however at a system level it may lead to greater power and processing time than the alternative.

The reason for this is that if you need flexible pre and/or post processing of data in addition to the primary data manipulation of the accelerator – you will find the application performing many CPU operations and many memory operation, in addition to the operation of the accelerator. The net result is that any advantage of the accelerator is offset by the overhead of pre and post processing.

WHAT DOES THIS HAVE TO DO WITH RISC-V?

Since RISC-V is both an Open and Extensible ISA – it means you can build an implementation that is compliant to the standard and as such able to take advantage of the rich software ecosystem (OS’, Libraries, etc) – while at the same time utilizing application specific processor optimization and extensions. Something that is not possible with a traditional ARM or MIPS processor.

The advantages of extensions rather than accelerators is that the main processor can do the needed data transformations in an highly efficient manner.

This means what would be in an accelerator context the following sequence

  • Processor Data read
  • Processor Data Pre Process
  • Processor Data write
  • Accelerator Init
  • Accelerator Data Read
  • Accelerator Data transform
  • Accelerator Data Write
  • Processor Data Read
  • Processor Data Post Process
  • Processor Data Write

Becomes

  • Processor Data read
  • Processor Data Pre Process
  • Processor Data Transform (via processor extensions)
  • Processor Data Post Process
  • Processor Data Write

The drastic reduction in system traffic reduces overall system complexity and power. This is not a new concept, but the advent of the extensible RISC-V architecture makes it easier than ever to achieve.

SO ARE EXTENSIONS ALWAYS THE ANSWER?

I would love to say yes, but that would put us back into the “everything’s a nail” situation. The reality is that it depends on your data and your application.
Thanks to the extensibility of the Codix-Bk Core (RISC-V compliant)  and the ease of modifying the implementation of RISC-V using Codix Optimizer you can easily decide if the best answer is an accelerator, or processor optimization/extensions. This is not something that has been possible previously. Sure there were extensible processors, but they locked you into a closed and limited ecosystem.

With Codasip and RISC-V you get the best of both worlds.

Karel Masarik

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BaySand, Codasip, Codeplay and UltraSoC accelerate IoT development with “silicon-to-intelligence” RISC-V platform


December 1, 2016

MOUNTAIN VIEW, CA, 29th November 2016

BaySand, Codasip, Codeplay and UltraSoC today announced an integrated IoT development platform based on the RISC-V open processor instruction set architecture (ISA).  The platform offers an open-standards-based solution that allows designers of systems-on-a-chip (SoCs) for IoT applications to get from concept to silicon with a high level of software integration in record time and substantially de-risks the entire product development process.

This new collaboration will be formally announced at the 5th RISC-V Workshop (Google Quad Campus, Mountain View, CA, 29th November), and combines the following partnership:

  • BaySand’s foundational IP and Metal Configurable Standard Cell (MCSC) technology
  • Codasip’s extensible Codix Bk RISC-V-compliant processor implementation
  • Codeplay’s ComputeSuite software development tools for open standards middleware, and
  • UltraSoC’s on-chip debug and analytics architecture

The result is an end-to-end development flow that supports the rapid evolution of IoT systems, enabling timely market entry, in-market feature enhancement and on-going usability and cost optimization, all at the price points demanded in this highly cost-sensitive market.

“RISC-V adoption is accelerating, and the IoT is clearly an arena where an open, independent processor architecture offers very powerful advantages,” said Caroline Gabriel, Research Director of ReThink Research. “But as with any processor architecture, the RISC-V ISA needs a healthy, co-operative ecosystem surrounding it: an ecosystem that puts designers in control and empowers innovation.”

Rick O’Connor, Executive Director of the RISC-V Foundation, commented: “A key part of our mission at the RISC-V Foundation is to bring technology developers together, in a standards-based environment, to build a robust ecosystem around the RISC-V ISA. We’re delighted to see these four leading firms in the RISC-V community coming together to offer such a powerful solution.”

The new platform leverages BaySand’s patented MCSC technology which delivers the power, performance and density advantages of standard cell ASIC technology while reducing NRE and time to market (TTM) and dramatically increasing design flexibility. The company’s UltraShuttle multi project wafers (MPW) and MetalCopy FPGA porting technology help to bring new designs to market quickly, with low risk: they combine with a proven and predictable design flow and a rich IP library to create an ideal solution for IoT class designs.

At the IP level, Codasip’s Codix-Bk IP cores are the industry’s first commercially available RISC-V compliant processors, and are at the heart of the new joint platform offering. They are available in multiple configurations and can be quickly and easily customized to the exact needs of IoT designs via unique application analysis technology and a model-based IP structure.

UltraSoC contributes silicon IP and software tools that enable secure, non-intrusive monitoring and analysis of IoT device behavior. These powerful features ease the task of writing and debugging the software that is intrinsic to the operation of complex ICs; they accelerate first-time bring up of new devices; and the same IP allows robust hardware-based security features that can detect unexpected behavior caused by bugs or by malicious interference (Bare Metal Security™).

At the highest level within the new platform, Codeplay provides developers with an open standards based programming model that extends from device-specific functionalities all the way up to highly abstracted machine learning paradigms such as Google’s TensorFlow. ComputeSuite extends the RISC-V platform with OpenCL™ and SYCL™ allowing applications to target the underlying hardware for highest performance, using standard APIs.

Partner quotes

  • Rupert Baines, CEO, UltraSoC: “We’re delighted to be coming together with three of the other key players in the RISC-V arena, BaySand, Codasip and Codeplay.  Our aim in this collaboration is to enable accelerated product development cycles, lower costs and more agile development, in particular for IoT designs. Our technology helps SoC developers across the chip and throughout the development flow, and this partnership reinforces the strength of that offering.”
  • Karel Masarik, CEO, Codasip: “This collaboration is an important one for our customers as they look to replace proprietary ISA’s with RISC-V. It allows them to quickly bring new SoCs to life, while providing functionality that exceeds what they have had access to in the past. Our Codix-Bk series of RISC-V processor IP, with its LLVM-based development environment, make integration quick and low risk, demonstrating the power of commitment to open standards.”
  • Ehud (Udi) Yuhjtman, EVP marketing and Sales at BaySand: “BaySand is a supporter of open source hardware and we are excited to be part of this great team that brings together an open source ISA complete solution.  This RISC-V implementation with the UltraSOC tools is a game changer that will enable designers and companies to design at an affordable budget their own efficient IoT ASIC and system. We are working on the ASIC implementation which will be available for evaluation to our customers and partners.  The complete solution and technology provides the ability to build custom designs with BaySand special UltraShuttle MPW and the Metal Configurable Standard Cell (MCSC)”.
  • Andrew Richards, CEO, Codeplay:  “Codeplay is excited to see RISC-V gaining in popularity and we are keen to ensure software developers are correctly equipped to host their software applications on it. Codeplay is working extensively with machine learning solutions such as Google with TensorFlow, and we will bridge the gap on RISC-V with the open standards OpenCL and SYCL.”

About UltraSoC

UltraSoC is an independent provider of SoC infrastructure that enables rapid development of embedded systems based on advanced SoC devices. The company is headquartered in Cambridge, United Kingdom. For more information visit www.ultrasoc.com

About Baysand

BaySand is the leader in application configurable ASICs targeting short time-to-market and cost-effective ASIC solutions. With its unique and patented Metal Configurable Standard Cell (MCSC) technology and Field Configurable DSP (fcDSP) architecture, the company provides ASIC designers with world-class solutions featuring low non-recurring engineering costs, short time-to-market, low power, low unit cost, high performance, programmability and flexibility. BaySand is fabless, privately held and based in the Silicon Valley, San Jose CA. For further information about BaySand, visit http://www.baysand.com.

About Codeplay

Codeplay is internationally recognized for expertise in open standards for heterogeneous systems and has many years of experience in the development of Compilers, Runtimes, Debuggers, Test Systems, and other specialized tools. Codeplay has delivered standards-compliant systems for some of the largest semiconductor companies in the world, focusing specifically on high-performance heterogeneous processor solutions for CPUs, GPUs, DSPs, FPGAs and specialized imaging and vision processors. Visit www.codeplay.com for more information

About Codasip

Codasip delivers leading-edge processor IP technology that provides the advantages of industry standard processor IP with the ability to optimize for your unique application. Codasip’s unique model-based processor IP, and application analysis technology, makes processor customization and optimization available to any design team. As a founding member of the RISC-V foundation (riscv.org) and long term supplier of LLVM and GNU based processor solutions Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe. More information on Codasip’s products and services is available at https://codasip.com.

Contacts

UltraSoC, Andy Gothard (andy.gothard@ultrasoc.com)

Codeplay, Charles Macfarlane (charles.macfarlane@codeplay.com)

Codasip, Neil Hand (hand@codasip.com)

Baysand, Joshua G (Joshua@baysand.com)

Kava

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