Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

How to reduce the risk when making the shift to RISC-VIn conversation with Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip


November 17, 2022

With the Intel® Pathfinder for RISC-V* program, Intel launched a development environment that enables companies of all sizes to start their RISC-V journey. Codasip makes its L31 RISC-V embedded core available to the embedded community through the program.

We asked Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip, to tell us more about this.

On the left: Rupert Baines – CMO at Codasip; on the right: Vijay Krishnan – GM, RISC-V Ventures, Incubation and Disruptive Innovation (IDI) Group at Intel Corporation

Vijay, what is the risk when making the shift to RISC-V?

There is real risk and then there is perceived risk. Regarding the former, any architectural transition adds complexity, but with RISC-V the entire hardware and software ecosystem is coming together in a manner which minimizes the real risk, while unleashing the long-term value that comes with an open, modular and modern instruction set architecture. The presence of cores like the Codasip L31 are making it easier and easier for customers to make that transition so they can reap the benefits of RISC-V. Sensors, security IP/software, IoT middleware and cloud connectivity available within the Intel Pathfinder for RISC-V IDE all help to mitigate perceived risk by demonstrating end-to-end capabilities at the pre-silicon stage.

Rupert, do you agree with this, and is RISC-V risky?

Well, the cool thing about RISC-V is that it is an open standard, and that brings so many possibilities. But that can also be a challenge! Endless possibilities make it harder to make a choice and the evolving ecosystem can be hard to navigate.

Intel has blazed a path with Intel Pathfinder for RISC-V by making a first selection of recommended vendors, and from that stamp of quality, companies can explore and evaluate what best fits their needs.

As a key RISC-V processor IP vendor, it was obvious for Codasip to be part of the Intel Pathfinder for RISC-V ecosystem. Our L31 core is quite versatile so we chose to make it available to the wider embedded community through the program. It is a low-power, general-purpose, embedded RISC-V core that balances performance and power consumption. From IoT devices to industrial and automotive control, or as a deeply embedded core in a larger system, it brings local processing capabilities into a compact area.

Who is going to benefit from this Intel & Codasip partnership?

Vijay: The initial beneficiaries are end-user segments addressed by the Codasip L31 core. Over time we hope Intel Pathfinder for RISC-V will include support from a broader range of Codasip cores. By harnessing our combined capabilities, we see a tremendous opportunity to accelerate the transition to RISC-V, thereby establishing it as a third mainstream compute architecture after x86 and Arm.  

Rupert: Companies of all sizes, really. From SMEs to start-ups and bigger players. We give everyone access to high-class silicon ready proof points to get started with their RISC-V journey in a standard and stable environment. If they wonder whether they should go with our L31 core, they can see their use case brought to life. With Intel Pathfinder for RISC-V, our core can be integrated with a growing set of complementary IPs, multiple operating systems, and toolchains for IoT and embedded applications.

Intel Pathfinder for RISC-V and Codasip logos

How is the RISC-V ecosystem doing today?

Vijay: In addition to being open and modular, RISC-V is free and easily licensable. In less than 10 years since its inception, RISC-V has made remarkable progress, driven largely by a well-knit ecosystem that includes academia & research in addition to a breadth of commercial organizations. The opportunities are vast, and based on what we have seen to date, the RISC-V market will reward organizations that not only build competitive products, but also foster collaborative models within the ecosystem.

Rupert: The RISC-V community is growing rapidly and continuously gaining market traction. It is attracting everyone, from university researchers to major industry players. There have been new processors and new ISAs in the past. But what is different about RISC-V is the ecosystem, a critical factor in the success of a processor architecture. More and more players are joining, more and more software and tools are available, broadening the adoption of the ISA. This in turn is attracting more ecosystem partners in an accelerating virtuous spiral, and it is that spiral that is driving the success of RISC-V, in which Intel and Codasip play a major role for the embedded industry.

How is this partnership helping companies make the shift to RISC-V?

Vijay: By combining Codasip RISC-V IP with the Intel Pathfinder for RISC-V developer tools, we are making it easier for customers to go from product concept to a mature platform that includes silicon and software. Intel Pathfinder for RISC-V combines RISC-V IP with complementary security IP, accelerators for AI/ML, Vision and Audio processing, as well as sensor and middleware integration, thus providing an accelerated software development path for customers that reduces time to market, cost and complexity/risk.

Rupert: The program removes the barrier to the adoption of RISC-V by providing a level of standardization that can make RISC-V adoption easy with some level of consistency for the software developer community. By collecting vendors of different types, the program can kickstart the development of a new system by bringing together all the great capabilities already out there, including L31. You can instantly start an IoT application based on our L31 core, combine it with other IP, integrate security from Crypto Quantique, and verify it all using Siemens EDA even before committing to silicon.

Collaboration is key.

Those who collaborate are better set for success in RISC-V than those who don’t. Thanks to an ecosystem coming together, the risk of RISC-V is reduced, and you can easily explore options when you are ready to make the shift. Codasip and Intel are exploring further possibilities for collaboration, and you will see more offerings going forward, always with quality and ease of use in mind.

Give it a try!

* © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. No product or component can be absolutely secure. 

Lauranne Choquin

Corporate Marketing Manager

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DAC 2022 – Is it too risky not to adopt RISC-V?


July 18, 2022

I was fortunate enough to attend the 59th Design Automation Conference (DAC) in San Francisco last week. Aside from the Covid closure in 2020 I’ve been going to DAC since 1995. Many people, including me, arrived to the San Francisco with a bit of trepidation. After all, 58th DAC had low attendance and it was only ~7 months ago. What was the DAC 2022 conference going to be like? How would Covid affect things? Would international travelers come to San Francisco?

Frankly, I was impressed! Yes, the exhibit hall is smaller than it used to be. Yes, the attendance is not what it was in the 2000’s… and yes, there were times where it was quite slow on the exhibit floor. At the end of the day the many international travellers did show up and the conference and exhibits were quite well attended. At Codasip we met with customers and prospects from all over the world — Korea, Japan, Europe, the US, and more.

The Codasip team at our booth
The Codasip team at our booth  

Moore’s Law continues to slow

I started the week on Sunday at the well-attended Needham analyst event with Charles Shi. Charles mentioned there were concerns about a semiconductor down cycle but thought that the EDA and IP companies could push through without too much trouble. Charles expanded on his talk from December 2021 noting that Moore’s Law continues to slow and this is, at least partially, driving wafer and transistor costs higher as transistor density is no longer doubling in each new node.

I latched onto a comment that Charles made — that leading systems companies were designing their own chips. Companies like Apple, Tesla, and others were beating Moore’s Law and differentiating their product by building their own custom chips.

Slide from Charles Shi's talk - System providers designing their own custom chips
Slide from Charles Shi’s talk – System providers designing their own custom chips

If scaling is no longer an option in most situations, optimization means customizing a processor for your specific application. The only way forward to differentiate is architectural innovation. If you haven’t already, I encourage you to look at our whitepaper on semiconductor scaling.

The demo at our booth showing the benefits of adding custom instructions on our L31 RISC-V core raised a lot of interest

The demo at our booth showed what Jon Taylor, our Director of Application Engineering, presented at Embedded World 2022 on customizing RISC-V cores to accelerate neural networks. You can watch his talk here.

Optimism around the industry, RISC-V, and Codasip

One of the highlights of my week was the executive dinner hosted by the Codasip management team. The intimate event included customers, partners, and industry supporters. We shared ideas, told stories, and had a lot of laughs together. There is nothing quite like having this time in person – the online meetings just can’t compare. One takeaway from that event was the optimism around the industry, RISC-V, and Codasip.

Executive dinner hosted by the Codasip management team

Is it too risky not to adopt RISC-V?

A couple of weeks ago, Embedded World 2022 showed us that the RISC-V genie is now out of the bottle. It was therefore no surprise to see that a key theme of this DAC was RISC-V. RISC-V appeared in papers, posters, presentations, tutorials, and in the exhibit hall. There were new university ideas, cool security projects, open-source and commercial implementations of RISC-V, and verification technologies, to name a few.

The question is no longer if RISC-V is too risky too adopt — but is it too risky not to adopt.

And companies are adopting RISC-V. The RISC-V International community is made up of over 200 companies from 50 countries. A quick search on Indeed.com shows over 400 job postings referencing RISC-V in the US alone. This doesn’t even include the dozens of jobs that Codasip has open!

One very interesting thing we heard at DAC is about John Deere designing their own ASICs to improve customer productivity and help to deliver more value to farmers. The company, by investing in building its internal capabilities around data science and analytics, is transforming into a data-driven technological manufacturing company. The John Deere Operations Center delivers value to farmers with tools and features that enable them to easily access farm information to better manage their daily operations. This article is a nice summary of how John Deere is leveraging AI, IoT and data analytics.

All in all, it was a great week at the Design Automation Conference. I’m certainly looking forward to the 60th DAC in 2023. It was great to see all of the new innovation in the industry and especially around RISC-V. RISC-V is here and the team as Codasip is proud to be leading the way with our unique approach to RISC-V.

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A European Opportunity for Codasip


March 10, 2022

Why did I join Codasip a couple of days ago as VP of Sales for EMEA? We could sit down here and discuss for a few hours, but perhaps I should keep it short for now. Number 1: The RISC-V revolution is happening and Codasip is one of the leaders in the industry. Number 2: The market opportunity is ripe. It is time we make sure the European semiconductor industry understands the value and Design for Differentiation offering from Codasip.

The RISC-V revolution is happening

Did you know that Codasip was founded in 2014 with the launch of Codasip Studio™, and that a year later it co-founded RISC-V International with other key players in the industry? And that same year, in 2015, Codasip launched its first RISC-V processor core? Codasip was definitely a pioneer of that revolution and is today a true leader with strong foundations to build on.

The semiconductor industry today thrives on innovation choice and diversity. Scaling is failing and the only way in the short-term is to take specialization further by creating innovative architectures and domain-specific accelerators for tackling specialized processing problems. Instead of the classic approach of tailoring software to available microprocessors it is now necessary to create hardware that is designed to match a software workload. This can be achieved through customizing an ISA, creating special microarchitectures, or creating novel processing cores and arrays. That’s exactly what RISC-V is perfect for.

With a portfolio of best-in-class quality processors and unique design automation technology, Codasip opens a new avenue for the industry. We enable processor customization in matter of months, allowing our customers to create the compute engine that is right for their algorithm. Across many use cases, this results in unparalleled advantages without compromising time to market.

Advanced processes cannot be the only answer to higher performance. Rethinking how processors can be altered so that they may be exploited to their full capacity for different uses cases is a disruptive and very elegant approach to overcoming performance, power, and cost bottlenecks. Codasip is the undisputed leader in this field. As our CMO Rupert Baines said, now is the right time to join Codasip and be part of the RISC-V revolution.

Right here, in Europe

Codasip is strongly anchored in Europe, and so am I. Codasip is definitively a global company but a strongly and strategically European in a way that sets it apart from its competitors.

Given the strategic importance of Europe in the global chip economy today, Codasip is in the right place at the right time to help bolster the region’s industry, and it is fundamental that our customers in Europe know that. On one hand, Europe is building its own initiatives to boost the semiconductor industry and to enhance its self-sufficiency. The European Chips Act is set to drive initiatives, Intel sees a strategic neutrality of Europe and is investing $20Bn in fabs in Germany plus Tower Fabs in Israel.

At a time when there is at least a short to mid-term shortage in the supply of chips, Europe’s initiatives are likely to strike a chord with the needs of the industry. Added to that, Codasip is strategically located in Europe making us well-positioned to work with Chinese or US companies.

With a strong portfolio of RISC-V processor IP and unique Studio custom design tools, companies of all sizes are able to quickly, easily and cost-effectively benefit from Codasip’s Design for Differentiation offering. There is work to be done in educating the EMEA market, but it is clear that Codasip delivers significant value.

Being French and British and having operated in this region most of my career, I cannot wait to work with key European customers in addition to the leading customers Codasip has all around the world, to enter long-term strategic partnerships as RISC-V is becoming the inevitable architecture computing is gravitating towards.

Emmanuel Till Vatier from Codasip

Emmanuel Till-Vattier

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RISC-V Summit 2021


December 17, 2021

We weren’t sure what to expect from our first major attendance at a #RISCVSummit. Although we were a founding member of RISC-V – as we’ve been saying quite a lot recently – we have been hiding our light under a bushel.

We’ve certainly been busy though – enabling over 2 billion RISC-V cores with our RISC-V processor IP and Studio tools while helping customers use architecture licenses, customization and domain specific compute – but perhaps we neglected the publicity.

CTO Zdeněk Přikryl presents RISC-V custom instruction session. Image source: Codasip.

However, we are now growing seriously and we know we can’t rest on our laurels. So off to San Francisco we trotted…A magnificent team of seven Codasippers were at the Summit, including a raft of our senior execs: new CEO Ron Black,  CRO Brett Cline and CTO Zdeněk Přikryl together with a US sales team and more. Mustn’t forget myself: CMO Rupert Baines!

With Omicron timed to spoil the party, the event’s attendance was never going to be the best ever. A lot of visitors sadly did have to cancel. But while numbers were down, there were still a lot of good meetings and great presentations. Interestingly, the Summit was busier than DAC with which it was co-hosted. DAC is of course a fundamentally important event in the design calendar, but it was clear that RISC-V still brings with it a sense of something new and exciting: a growth opportunity. And who doesn’t love a growth opportunity.

For those of us from outside USA it was also a great opportunity to meet customers face-to-face even if they were not at the event. Doing business over Zoom has been efficient but there is something magic that happens with a CTO, a whiteboard and an engaged customer architect.

Meanwhile, Filip enjoyed his first US trip and clocked up his tourist points.

Image source: Codasip.

Ron’s presentation on the end of scaling and need for heterogenous compute was particularly well-received – with plenty of nodding heads in the audience. Watch the video recording of ‘Scaling is Failing’ keynote address here. Ron recently put his thoughts into a blog

Ron Black, CEO. Source: Codasip.

The Summit saw some new entrants into the RISC-V ring. It is great to see the growing interest in RISC-V – although you could say they’re late to a party that’s now well and truly underway! We know from our own experience that there are no shortcuts to catch-up.

There were also new launches from existing RISC-V vendors, but from our perspective nothing that changes our outlook nor our prospects on selling our next 2 billion cores.

Our friends at Imperas were making a very good point on the need for better verification in RISC-V – something we passionately believe in (and it was incredible how some people seem not to appreciate). Watch the Imperas RISC-V verification presentation here.

The fact is, the RISC-V market is ripe for domain specific designs, as Ron made clear from his presentation: Dennard, Moore’s, Amdahl’s,..these traditionally immutable laws of semiconductor design and scaling are, well, mutable!

If you missed the event, watch the presentation from Ron Black, Zdeněk’s 10 minute overview to custom instructions in RISC-V and contact us directly to find out how we can help you design the best possible processors to differentiate your product in an increasingly competitive marketplace.

Rupert Baines

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Scaling to new heights at Codasip


December 2, 2021

Scaling is failing is a drum we’re banging here at Codasip: the end of Moore’s Law, Dennard Scaling, Amdahl’s limits… Semiconductor process shifts are costing more but no longer providing the expected and required performance improvements.

Something must be done, and fortunately there is RISC-V with its open ISA that lets designers tune not only the microarchitecture, but the ISA itself, to co-develop hardware and software and provide truly optimized performance, power, and area. Codasip’s Studio™ EDA tool and CodAL processor description language are arguably the easiest and most proven way to make such customization.

Image source: Codasip.

Customers today are telling us that they want more “heterogeneous compute” and “domain specific acceleration”, a topic covered by our CMO Rupert Baines in a post about Apple’s recent M1 Pro launch.

And this is exactly the Design for Differentiation Codasip is providing for our customers. Our incredibly supportive existing and new investors are committed for the long-term to expand Studio, CodAL, and our portfolio of RISC-V cores to include the high-end and new functionality we will unveil in the coming quarters.

As we keep saying, Codasip has been a well-kept secret, but will not be for much longer. Indeed, our customers have already deployed an estimated 2 billion cores designed with Codasip tools!

Dr Ron Black was appointed as Codasip’s CEO today (2 December 2021), read the news here.

Ron Black, CEO. Source: Codasip.

If you want to hear more about #ScalingIsFailing, come along to my #RISCVSummit keynote on Wednesday, December 8th at 14:10 PST (that’s 2210 GMT/UTC), find out more on our RISC-V Summit 2021 page – hope to see you there, in person or virtually.

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Why it’s the perfect time to join Codasip and be part of the RISC-V revolution


September 13, 2021

Eighteen months ago, I said: “The rise of RISC-V offers us a tremendous platform for innovation and collaboration: it has the potential to change the business model of the entire industry.” I stand by that and indeed am demonstrating my conviction by joining the ranks of a company that’s not only changing the industry business model, but is significantly innovating in RISC-V.

Having taken UltraSoC to its exit (sold to Siemens in June 2020), I was on the lookout for the next opportunity. It didn’t take research to know I wanted to be part of RISC-V. And Codasip has an incredibly strong team I know and respect – having worked with them, via our partnership at UltraSoC, or having known through previous roles in the industry. I jumped at the opportunity to work with a European company in such a strong market position.

Codasip is like other RISC-V IP vendors in that we have a portfolio of standard cores for those who want a standard product. But we have something unique: the custom capabilities of Codasip Studio that take the open-market opportunities of RISC-V to a new level. This radically simplifies the task of differentiation and offering our customers the ability to embed unique features. This creates a virtual bridge for those companies who want the ecosystem of a standard ISA, but also want the flexibility of a custom-designed processor.

The industry momentum and interest in RISC-V continues to grow, unabated… in fact, with even more impetus. Why is this? Well, as I’ve long since preached (I’m told I preach!) since its inception, RISC-V has represented a fundamental shift in the industry – a shift in processor architecture that is only just starting.

Arm has transformed the industry and still (rightly) has a significant following for its architecture. But no-one can deny there are questions over where the company is heading and concern over the implications and longer-term design choices. That is opening up the market to the benefit of SoC designers and the industry as a whole – and, of course, to the benefit of alternative solutions like Codasip.

This is a timely opportunity for RISC-V. And Codasip, with its Studio platform, finds itself at the sweet spot: offering customers all the benefits of the open-standard RISC-V ecosystem combined with the ability to customize and differentiate their designs. This is the best of both worlds – offering a unique value to a significant portion of the market.

Codasip’s proposition means it already has excellent customer traction – it was one of the first companies to commercialize RISC-V IP – but the fact it remains (mostly) a well-kept secret is, from my point of view, a marketing dream come true and a challenge I relish!

Rupert Baines

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Is RISC-V the Future?


July 27, 2021

Is RISC-V the future? This is a question that we often get asked, and let’s assume that we mean ‘is RISC-V going to be the dominant ISA in the processor market?’. This is certainly an unfolding situation and has changed significantly in the last five years.

What is RISC-V and what does RISC-V do?

RISC-V originated at the University of California, Berkeley, in 2010 and took a number of years to get traction with industry. A big step forward was the formation of the RISC-V Foundation in 2015 as a non-profit organization to drive the adoption of RISC-V. In early 2020, the RISC-V Foundation activity was re-branded and re-incorporated as the Swiss-based RISC-V International.

I remember exhibiting at Embedded World in 2017 and the Codasip stand had the RISC-V logo prominently displayed. Many visitors asked, “what is RISC-V?”, showing that awareness in Europe was low. Since then, the situation has changed dramatically with a high level of interest in all geographies.

For many years, we have tended to classify processors into silos such as MPU, MCU, GPU, APU, DSP, etc. Some devices, such as mobile phones, would combine multiple types of processor cores in their designs. If we think back to, say, 2016, the MPU world was dominated by the X86 architecture while Arm dominated both APUs (application processors and the mobile phone ecosystem generally) and MCUs.

Is RISC-V better than Arm? Is RISC-V better than x86 from Intel/AMD? It definitely is different and brings new opportunities. Today we can identify a few new trends in the market that RISC-V is enabling. Let’s look at 3 of them.

Trend 1: RISC-V is shifting up in performance

In the early years of RISC-V, it was mainly used on academic projects. However, by 2016 a wide range of commercial companies were developing embedded microcontrollers based on the RISC-V ISA. It could be argued that this was a relatively easy step for the RISC-V community, given that embedded developers are used to building their systems from a variety of sources, including middleware delivered as source code. Also embedded cores are simpler in complexity.

RISC-V processor performance trending upwards. Source: Codasip.

What is more challenging is moving into application processors, with considerably more complexity required to support rich operating systems such as Linux or Android. In the case of mobile phone applications, there is a complex ecosystem which will take a while for RISC-V vendors to support. Nevertheless, there are plenty of other opportunities for RISC-V application processors in systems which use Linux, and there is a choice of IP cores such as Codasip’s A70 addressing mid-range performance.

Finally, we can expect more and more suppliers to create complex RISC-V cores for high-performance computing in the future.

Trend 2: RISC-V is breaking down the barriers between processor types

With semiconductor scaling failing, the boundaries between traditional processor grouping are blurring. With more and more demand for domain specific accelerators to achieve cost-effective performance on-chip, it is more and more necessary to tune the design to the needs of the workload required.

With the RISC-V ISA, having a minimalist base integer instruction set and providing for custom extensions, it is an ideal starting point for creating special accelerators.

While some applications, such as mobile phones, with complex legacy software are unlikely to change architecture in the short term, others have no constraints. New applications, such as  AI (artificial intelligence), are moving to RISC-V as the open ISA with flexibility and customization. And in a more distant future, RISC-V has the potential to gain even greater market share as legacy considerations cease to apply.

Trend 3: Customers want to avoid a monopoly supplier

Finally, there is a strong desire for change in the processor market. Since the 1980s, microprocessors have been dominated by the Intel/AMD X86 duopoly, but in the late 1990s, Arm became the de-facto standard in the mobile phone processor market. That monopoly extended further into adjacent areas, including embedded.

For the last decade, I have often heard engineers talk of “Arm fatigue” and disquiet with the monopolist position and vendor lock-in in key markets. However, as long as Arm could claim ‘Swiss neutrality’ with their broad product range, nobody would be fired for licensing Arm. With their acquisition by SoftBank, that neutrality was seriously eroded, and the now failed Nvidia merger attempt unsettled many licensees.

The free and open RISC-V ISA has seen widespread interest and is likely to be a catalyst for a sea change in the market. As an open standard, it has the potential to be relevant for decades, and with multiple suppliers offering processor cores, it avoids vendor lock-in.

RISC-V shipments predicted to grow strongly. Source: Semico Research Corporation.

While nobody expects architectures with a rich history – such as X86 or Arm – to disappear overnight, for the first time in decades designers have a viable alternative in RISC-V. With RISC-V covering a greater and greater range of performance and having a rapidly expanding ecosystem, the market share for RISC-V will continue to grow. This is reflected by market reports such as Semico Research, predicting that the market will consume 62.4 billion RISC-V CPU cores by 2025.

RISC-V surely has a rapidly growing future and a great chance of being a dominant architecture.

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Codasip Presence at Upcoming Events: China Roadshow, DAC 2019, and RISC-V Workshop Zurich


May 6, 2019

Munich, Germany – May 6th, 2019 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, is going to be featured at three major industry events around the globe in the second quarter of 2019: China Roadshow 2019, Design Automation Conference in Las Vegas, and RISC-V Workshop in Zurich.

 “Getting Started with RISC-V” Roadshow 2019, May 6–16, is a series of events taking place in five cities across China in eleven days. The show aims to present entry-level examples of innovative RISC-V solutions, and attendance is free of charge. Codasip is co-sponsoring the event and will have Tina Xiang, China General Manager, speaking about Codasip’s smart solutions and tools for automated generation and customization of RISC-V processors. Tina’s presentation starts at 10:00 each day of the main show schedule:

  • Wednesday, May 8, Sheraton Chengdu Lido Hotel
  • Monday, May 13, Hyatt on the Bund, Shanghai
  • Tuesday, May 14, JW Marriott Hotel Hangzhou
  • Thursday, May 16, Crowne Plaza Zhongguancun Beijing

More information about the RISC-V Roadshow China is available on the official event website.

Design Automation Conference 2019, June 2–6 at the Las Vegas Convention Centre in Las Vegas, Nevada, is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and intellectual property (IP). The event will offer close to 300 technical presentations, training sessions, workshops, and an exhibition area featuring of around 200 companies. Codasip’s VP of Worldwide Sales, Jerry Ardizzone, will be presenting his views on the future commercial success of open ISAs as a guest of a panel discussion on Tuesday, June 04, at 10:30. Detailed information on the discussion topic is available on the official DAC 2019 website.

RISC-V Workshop Zurich, June 11–13 at ETH Zurich (Swiss Federal Institute of Technology), is organized by the RISC-V Foundation and again co-sponsored by Codasip. The presentation will be given by Zdeněk Přikryl, Codasip CTO, who will explain the benefits of the open source compiler technologies developed within the LLVM project, and how Codasip integrates the LLDB debugger in its automated toolchain. His presentation is scheduled for Wednesday, June 12, at 17:40. More information about the presentation is available on the official RISC-V Workshop website.

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About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and

GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. For more information about Codasip’s products and services, visit www.codasip.com.

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. For more information about RISC-V, visit www.riscv.org.

Kava

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Codasip to Demonstrate Technology Leadership and Commitment to Open Standards at Taiwan RISC-V Workshop


March 7, 2019

Munich, Germany – March 7th 2019 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, will address the topics of RISC-V C compiler optimizations and frameworks for ISA compliance in two presentations at the upcoming RISC-V Workshop in Taiwan.

In the first presentation, Codasip CTO Zdeněk Přikryl will demonstrate how Codasip generates and optimizes the latest LLVM version 7.0.1 toolchain to make use of custom instructions, including debugging and profiling. The LLVM project continues to expand rapidly as industry leaders have chosen to adopt LLVM compiler due to its excellent quality of results. While many employ various components of the LLVM toolchain, Codasip has announced availability of LLVM for compilation, code generation, and debugging for its family of RISC-V processors. Full support for LLDB in command-line mode or as part of an Eclipse-based graphical debug is now part of its latest generation of licensable software development tools.

In the second presentation, Codasip engineer Milan Skála will discuss requirements for a RISC-V compliance test framework that could be employed for any valid implementation of the RISC-V standard. He will show Codasip’s methodology as an example. Based on Python’s pytest, it provides golden reference model configuration, including test suite builds along with test suite parametrization, compilation, run control with results evaluation, and compliance test reports.

Karel Masařík, Codasip’s founder and CEO, said: “By addressing the topics of compiler optimizations and ISA compliance testing, Codasip is emphasizing its commitment to open standards for embedded processors. We are dedicated to making meaningful contributions to the RISC-V community to ensure that the ecosystem grows and benefits the entire industry. At the same time, we will of course continue to innovate with our own Codasip Studio which allows for rapid development of optimized and differentiated processor IP.”

The RISC-V Workshop Taiwan takes place on 12–13th March 2019 in the Ambassador Hotel, Hsinchu City, Taiwan. More information about registration and agenda can be found at the event webpage: https://tmt.knect365.com/risc-v-workshop-taiwan/

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information, visit www.riscv.org.

Kava

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