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Does ISA ownership matter? A Tale of Three ISAs


December 22, 2020

An instruction set architecture (ISA) is crucial to the development of processors and their software ecosystems. In the last half century, the majority of ISAs have been owned by single companies, whether product companies for their own chips/systems or processor IP companies who licensed their processors to chip developers. Does ISA ownership matter? Let’s consider three proprietary ISAs and their history.

Firstly, the Alpha ISA was developed by Digital Equipment Corporation (DEC) for its workstations and servers and was released in 1992. In the mid-1990s, this was considered a worthy competitor to SPARC and MIPS RISC architectures. However, the ownership of the ISA transferred to Compaq when DEC was acquired in 1998. Compaq in turn sold the rights to the Alpha ISA to Intel in 2001, and in the same year Compaq was acquired by Hewlett Packard. The last Alpha-based products were released in 2004, meaning that the ISA was effectively dead because of a series of acquisitions.

MIPS Technologies was spun out of Silicon Graphics as an independent IP company in 1998. For some years it enjoyed some success, particularly at the higher end of the processor IP market, and was only the second architecture to have Android ported in 2009. However, with a declining share price, MIPS sold 498 patents to AST and agreed to an acquisition by Imagination Technology in 2013. After Canyon Bridge acquired Imagination, MIPS was spun-out again ending up, after a series of transactions, as part of Wave Computing. As an artificial intelligence silicon provider, Wave is a potential competitor to some MIPS licensees.

Wave tried to encourage the adoption of the MIPS ISA in competition to RISC-V through their MIPS Open Initiative in late 2018. However, the licensing terms contained some onerous conditions relating to patents. In late 2019, Wave suddenly shut down the program, giving zero notice. The important lesson is that even if an ISA is open, its future is not secure if it is commercially owned. Seven years of ownership change have seen MIPS’ market share spiral downwards.

The third example is Arm, the biggest processor IP company of them all. Arm has long been seen as not only a big, successful IP company, but one offering “Swiss neutrality” in the semiconductor industry. Arm was quite distinct from both semiconductor companies and EDA companies. As such, it enjoyed a position of trust from its licensees as it did not have a conflict of interest. With its acquisition by SoftBank in 2016, Arm lost control over its destiny, even though SoftBank was not competing with its licensees. With the planned acquisition of Arm by NVIDIA, announced in September 2020, Arm will lose its neutrality completely. As a semiconductor company, there is a conflict of interest between Arm’s owners and its licensees, meaning it can no longer be trusted in the same way.

As can be seen from the ‘Tale of three ISAs’, the ownership of an ISA matters a lot, regardless of whether the ISA is commercially licensed or open. Acquisitions can lead to the disappearance of an ISA through merging of product lines or through making licensing difficult. Another motive for taking over a company can even be to kill off a competing product line, which in the case of an ISA could catastrophically impact licensees.

ISA ownership is one of the key issues that the developers of RISC-V have thought about. By transferring the ownership of the ISA to RISC-V International, the original developers of the ISA have assured its longevity. Longevity is assured both by the independent ownership of the ISA and the fact that licensees have a choice of IP vendors supporting the same open standard. Thirdly, once ratified, the ISA is frozen assuring software developers that their code will be able run on suitable cores indefinitely.

Roddy Urquhart

Roddy Urquhart

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Open Source vs Commercial RISC-V Licensing Models


November 26, 2020

Everybody is familiar with commercial licensing from traditional processor IP vendors such as Arm, Cadence, and Synopsys. But in discussing the RISC-V Open Instruction Set Architecture (ISA), there is widespread confusion of terminology with RISC-V often being described as “open source”. Some have even accused vendors of commercial RISC-V IP such as Codasip or Andes as not being in the spirit of RISC-V. But what is reality? What does the RISC-V licensing model for processor IP look like?

What does open source, open standard and commercial mean?

Let’s look at definitions briefly. An open standard like C, Verilog or HTTP is defined by a document that is maintained by an independent organization. Thus, C is maintained by ISO, Verilog by IEEE, and HTTP by IETF. These organizations maintain the technical standards using a set of impartial rules. Such open standards are generally freely accessible.

With open source, the source code for a software package or the hardware description language source for a hardware block are made available using a license. Open-source licenses vary from restrictive ones, such as copyleft license, to permissive ones, such as Apache. An open-source license defines rights for using, studying, modifying, and distributing the code. A copyleft license will require that any modifications be open-sourced, while a permissive license will not.

RISC-V is an open standard, and the ISA does not define any microarchitecture or business model. Therefore, a RISC-V microarchitecture can be licensed either as a commercial IP license or as an open source one. Nothing is prescribed.

If we think of a classic commercial processor IP license, you are generally paying for:

  •       The right to use the vendor’s ISA
  •       The right to use the vendor’s microarchitecture
  •       A warranty
  •       Vendor commitment to fix errors
  •       Indemnification

In practice, the warranty is usually time-bound, and the indemnification is limited. However, for the licensee, the vendor has some commitments to fix a design if bugs are found, which is valuable particularly on a tight schedule. If a licensee is accused of patent infringement, intellectual property indemnification means that the vendor will either defend the accusation or settle it on behalf of the licensee.

Traditional architecture and IP licensing model vs. RISC-V licensing model

Classic IP vendors have jealously guarded their own ISAs as well as their microarchitectures. A normal license bundles the use of the ISA with the microarchitecture and there are no rights to modify the deliverables. Very rarely such vendors have offered an architectural license which has enabled the licensee to use the ISA with their own microarchitecture, but such licenses have commanded substantial fees. One reason why RISC-V is very disruptive is that with a free and open ISA, one of the most valuable possible deliverables has no license fee.

Is RISC-V free? Open-source and commercial RISC-V based IP cores

Given that RISC-V does not prescribe microarchitecture or how it is licensed, there are both commercially licensed and open-source RISC-V IP cores. With an open-source license, you pay no license fee for the microarchitecture, but you also do not get all the benefits of a commercial license. Generally, deliverables have no warranty and are accepted “as is”. Similarly, there is not the indemnification that exists with a commercial license. If bugs are found, then either the licensee or the open-source community needs to fix them.

With commercially licensed RISC-V cores, the only fees are associated with the microarchitecture as the RISC-V ISA is licensed free of charge. With this license, you get the warranty, indemnification and bug fixing commitments normally associated with a commercial license.

What is the right licensing model for RISC-V?

We often get the question “Is RISC-V really open source?”. RISC-V is an open standard that allows companies to create RISC-V microarchitectures. Companies can then license the IP as either open-source or commercial. Which is the right choice for RISC-V? Both commercial licenses and open source licenses have advantages and disadvantages. You need to weigh up what is best for your design project.

At Codasip, we offer commercial RISC-V IP licenses and Codasip Studio technology that enables our customers to modify both the microarchitecture and the architecture.

In the past, commercial and open source licenses were seen as bitter competitors. However, in the software world, companies such as Microsoft have embraced both models. Microsoft offers commercial licenses, supports open source projects, and has cloud-based business models. Commercial and open-source RISC-V licenses can co-exist and complement each other.

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Codasip’s Expanding RISC-V Offering


July 22, 2020

Watch as video

In the last three months, Codasip’s RISC-V processor offering has expanded considerably. For some years, Codasip has supplied Bk3 and Bk5 RISC-V cores aimed at low- to medium-complexity embedded applications. But recently four additional cores have joined the Codasip RISC-V offering.

Three of the cores, the SweRV Core™ EH1, EH2 and EL2, were designed by Western Digital and were open-sourced through CHIPS Alliance. These 32-bit cores are mainly aimed at high-performance embedded applications and complement the existing 32-bit Bk3 and Bk-5 cores. The EH1 offers outstanding embedded performance due to its superscalar, dual issue architecture. Even more performance is delivered by the EH2 which provides two hardware threads (harts). The EL2 core is more compact and is a single-issue core.

The RTL for all three SweRV Cores is available on GitHub free of license fees. However, RTL alone is not sufficient to use a SweRV Core in an SoC design. Firstly, a complete software toolchain is needed to allow embedded software to be developed. Secondly, a comprehensive EDA design flow needs to exist to undertake simulation, static analysis, and synthesis of the core’s RTL. It is important that the core can be easily integrated with peripherals, memories, and buses in order to implement a sub-system. EDA design flows need to keep up with revisions in both the processor IP and the EDA tools.

In December 2019, Western Digital and Codasip announced that they were cooperating to enable the deployment of open-source SweRV Cores in production silicon. Codasip’s SweRV Core Support Package (SSP) provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip, including but not limited to verification testbenches and intellectual property, reference scripts for leading EDA flows, models for simulation and emulation, and software development tools.

The Support Package is available in a Free version consisting of open-source components and mainly aimed at academic use, and in a Pro version aimed at commercial SoC design using commercial EDA tools. The SweRV Core Support Package for EH1 was released in April and support for EH2 and EL2 was added in June. In addition, Codasip offers services for customizing SweRV Cores.

Although the semiconductor industry regularly talks of comparing processor cores in terms of performance versus complexity or in terms of PPA (performance, power, area), both performance and complexity have different aspects. Many Systems-on-Chip (SoCs) use multiple cores and face different requirements for different functions. For example, a core for a subsystem such as Wi-Fi will have quite different needs to one running a feature-rich OS such as Linux.

The Codasip Bk7 RISC-V core, announced yesterday, is Codasip’s first application processor. Like all previous Bk core designs, it has been designed in the Codasip Studio processor design system. This means that its architecture can be readily modified to create application-specific processors.  It has all the features needed for running embedded Linux and will be the cornerstone for further application processor developments. The Bk7 core is a 64-bit core with a 7-stage pipeline and memory management unit (MMU). Future versions of the Bk7 will support symmetric and heterogenous multi-processing.

In future posts we will be looking into some of the different facets of processor performance and complexity in order to see how the expanded Codasip offering can be applied to varying applications. We will also provide more detailed information on the Bk7 processor core.

 

Roddy Urquhart

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The Challenges of Making Open-Source RISC-V Deployment Effective


April 17, 2020

In an earlier post we pointed out that there may be hidden costs associated with deploying an open source RISC-V core. In the software world, Linux became a mainstream enterprise operating system when Red Hat provided a commercially supported distribution with professional support services. Western Digital and Codasip have had a similar vision to create a package that would enable companies designing chips to use the open source RISC-V SweRV Core™ family in an easy-to-use and low-risk manner.

There are some differences between deploying a RISC-V core in a chip and using Linux as an enterprise operating system. Let’s look at the challenges:

  1. For commercial chip design, the chances are that most design teams do not use open-source EDA tools; they use commercial tools for verification, synthesis and static analysis. These tools are from a variety of suppliers and the teams may even want to swap the tool used for a particular task from time to time. Also, designers may use a variety of Linux distributions on their computers. A challenge for using the open-source RTL is to be able to undertake design tasks effectively, regardless of the EDA tool chosen.
  2. Any core embedded in a system-on-chip (SoC) will require embedded software, and the software development needs to run in parallel with the SoC development. Again, teams need not only a suitable toolchain but also access to an instruction set simulator (ISS) and, in many cases, FPGA emulation.
  3. Ideally, hardware and software design teams should have a package capable of meeting the requirements of all aspects of using the core. Such a package needs to be robust, having had adequate testing, and be easy to deploy. It also needs to be maintained, as EDA and software development tools are updated regularly and the package needs to be able to work with current versions.
  4. Last but not least, IC designers and embedded SW developers need professional support through means such as support tickets, phone calls and even on-site visits to be sure that help is available when needed, otherwise the risk of exceeding budget and not meeting the deadline is high.

In case of Western Digital’s open SweRV Core, all these challenges are going to be solved by the SweRV Support Package which was pre-announced in December 2019. Since then, Codasip and Western Digital have been working on it diligently, developing components and combining them with existing open-source tools for a unique result. The package is going to provide a comfortable, ready-to-use integrated environment and all the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip. This will include not only the currently available SweRV Core EH1 but also the next SweRV Cores EH2 and EL1. Watch this cool short video by Western Digital’s Zvonimir Bandić to get a taste of the SweRV cores and the Support Package!

Roddy Urquhart

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Have you checked the hidden costs of deploying an open source RISC-V core?


April 9, 2020

It is often implied that if you use an open source processor core there are no costs associated with using it. Of course, the RTL may be free of a license fee and royalties and it might be possible to access a free of charge toolchain for RISC-V, but there are plenty of hidden costs associated with using the core in a real integrated circuit design.

If you are using the core in a production design, you are almost certainly wanting to use commercial EDA tools for verification, synthesis and static analysis checks. You also need to start developing your embedded software and will need access to a suitable instruction set simulator and/or FPGA emulation. Ideally, you will also want to access comprehensive documentation and customer support for using the core. A lot of elements are needed to successfully use the core in your design.

The bottom line is that none of the above activities are supported by simply accessing the open source RTL. It is possible to set up all of them from scratch but that comes with a significant engineering cost. It is important to count this cost of ownership before embarking on using an open source core. In reality, like an iceberg, the dominant costs are hidden.

There was a similar situation almost 30 years ago, when Linus Torvalds initially distributed Linux as floppy disk images. The installation procedure was complicated, and many early users struggled with it. The Linux world solved the problem by creating distributions that were much easier to use. What can be done to achieve the same for open source RISC-V cores? The answer to this question is just beginning to unfold.

Roddy Urquhart

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Does RISC-V mean Open Source Processors?


August 8, 2017

“RISC-V means open-source processors.” This is a statement that I have often heard this year – however, is it true or false? The answer is in this blog post.

Do open standards automatically mean open source?

Before answering the question “Does RISC-V Mean Open-Source Processors?”, let’s consider the broader issue of whether open standards automatically mean open source.

Open standards are widespread in technology. The communication protocols TCP/IP have been an open standard for decades. In wireless communication, Wi-Fi and Bluetooth are open standards with multiple versions.

In IC design, Verilog is an open standard maintained by the IEEE, and a widely used hardware description language. Verilog is used by a variety of commercial and open-source simulators. Incisive, Questa, and VCS are examples of well-known commercial simulators supporting Verilog, however Verilator & Cver are examples of open-source Verilog simulators. Generally, the commercial Verilog simulators are recognized for their high quality and performance.

RISC-V based processors can be either open-source or commercial

An open standard certainly does not rule out commercial products that use the standard. In the case of RISC-V, only the Instruction Set Architecture is standardized, leaving the microarchitecture and implementation to the processor developer. This gives ample opportunities for commercial processor cores. Commercial processor IP cores based on RISC-V will have their own features and value-add for example in microarchitecture and implementation.

Although there are open-source RISC-V processor cores including Zscale, Rocket, and BOOM from the University of California Berkeley, there are also commercial processor cores, such as Codasip RISC-V based processors.

Roddy Urquhart

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