Codasip to Offer Secure Boot Solutions with Veridify Tools

Codasip and Veridify Security, a leader in securing and managing low-resource devices at the edge of the IoT, announce they have partnered to provide secure boot functionality for the Codasip Low Power Embedded RISC-V processors.

Menta eFPGA and Codasip Announce Technology Partnership

Codasip announces a partnership with Menta S.A.S, a premier supplier of embedded FPGA solutions, enabling joint customers to modify processors in SoC after already manufactured. This will be possible by extending an existing processor with custom instructions in Codasip Studio and implementing these changes on Menta’s co-extended eFPGA cores.

Codasip’s Expanding RISC-V Offering

In the last three months, Codasip’s RISC-V processor offering has expanded considerably. For some years, Codasip has supplied Bk3 and Bk5 RISC-V cores aimed at low- to medium-complexity embedded applications. But recently four additional cores have joined the Codasip RISC-V offering.

What is SweRV Core EH2?

In mid-May, CHIPS Alliance announced the open sourcing of the SweRV Core™ EH2 and SweRV Core EL2 designed by Western Digital. These cores, as well as the earlier EH1, are now supported by Codasip’s SweRV Core Support Package which provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip. But what is SweRV Core EH2?