Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

How to reduce the risk when making the shift to RISC-VIn conversation with Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip


November 17, 2022

With the Intel® Pathfinder for RISC-V* program, Intel launched a development environment that enables companies of all sizes to start their RISC-V journey. Codasip makes its L31 RISC-V embedded core available to the embedded community through the program.

We asked Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip, to tell us more about this.

On the left: Rupert Baines – CMO at Codasip; on the right: Vijay Krishnan – GM, RISC-V Ventures, Incubation and Disruptive Innovation (IDI) Group at Intel Corporation

Vijay, what is the risk when making the shift to RISC-V?

There is real risk and then there is perceived risk. Regarding the former, any architectural transition adds complexity, but with RISC-V the entire hardware and software ecosystem is coming together in a manner which minimizes the real risk, while unleashing the long-term value that comes with an open, modular and modern instruction set architecture. The presence of cores like the Codasip L31 are making it easier and easier for customers to make that transition so they can reap the benefits of RISC-V. Sensors, security IP/software, IoT middleware and cloud connectivity available within the Intel Pathfinder for RISC-V IDE all help to mitigate perceived risk by demonstrating end-to-end capabilities at the pre-silicon stage.

Rupert, do you agree with this, and is RISC-V risky?

Well, the cool thing about RISC-V is that it is an open standard, and that brings so many possibilities. But that can also be a challenge! Endless possibilities make it harder to make a choice and the evolving ecosystem can be hard to navigate.

Intel has blazed a path with Intel Pathfinder for RISC-V by making a first selection of recommended vendors, and from that stamp of quality, companies can explore and evaluate what best fits their needs.

As a key RISC-V processor IP vendor, it was obvious for Codasip to be part of the Intel Pathfinder for RISC-V ecosystem. Our L31 core is quite versatile so we chose to make it available to the wider embedded community through the program. It is a low-power, general-purpose, embedded RISC-V core that balances performance and power consumption. From IoT devices to industrial and automotive control, or as a deeply embedded core in a larger system, it brings local processing capabilities into a compact area.

Who is going to benefit from this Intel & Codasip partnership?

Vijay: The initial beneficiaries are end-user segments addressed by the Codasip L31 core. Over time we hope Intel Pathfinder for RISC-V will include support from a broader range of Codasip cores. By harnessing our combined capabilities, we see a tremendous opportunity to accelerate the transition to RISC-V, thereby establishing it as a third mainstream compute architecture after x86 and Arm.  

Rupert: Companies of all sizes, really. From SMEs to start-ups and bigger players. We give everyone access to high-class silicon ready proof points to get started with their RISC-V journey in a standard and stable environment. If they wonder whether they should go with our L31 core, they can see their use case brought to life. With Intel Pathfinder for RISC-V, our core can be integrated with a growing set of complementary IPs, multiple operating systems, and toolchains for IoT and embedded applications.

Intel Pathfinder for RISC-V and Codasip logos

How is the RISC-V ecosystem doing today?

Vijay: In addition to being open and modular, RISC-V is free and easily licensable. In less than 10 years since its inception, RISC-V has made remarkable progress, driven largely by a well-knit ecosystem that includes academia & research in addition to a breadth of commercial organizations. The opportunities are vast, and based on what we have seen to date, the RISC-V market will reward organizations that not only build competitive products, but also foster collaborative models within the ecosystem.

Rupert: The RISC-V community is growing rapidly and continuously gaining market traction. It is attracting everyone, from university researchers to major industry players. There have been new processors and new ISAs in the past. But what is different about RISC-V is the ecosystem, a critical factor in the success of a processor architecture. More and more players are joining, more and more software and tools are available, broadening the adoption of the ISA. This in turn is attracting more ecosystem partners in an accelerating virtuous spiral, and it is that spiral that is driving the success of RISC-V, in which Intel and Codasip play a major role for the embedded industry.

How is this partnership helping companies make the shift to RISC-V?

Vijay: By combining Codasip RISC-V IP with the Intel Pathfinder for RISC-V developer tools, we are making it easier for customers to go from product concept to a mature platform that includes silicon and software. Intel Pathfinder for RISC-V combines RISC-V IP with complementary security IP, accelerators for AI/ML, Vision and Audio processing, as well as sensor and middleware integration, thus providing an accelerated software development path for customers that reduces time to market, cost and complexity/risk.

Rupert: The program removes the barrier to the adoption of RISC-V by providing a level of standardization that can make RISC-V adoption easy with some level of consistency for the software developer community. By collecting vendors of different types, the program can kickstart the development of a new system by bringing together all the great capabilities already out there, including L31. You can instantly start an IoT application based on our L31 core, combine it with other IP, integrate security from Crypto Quantique, and verify it all using Siemens EDA even before committing to silicon.

Collaboration is key.

Those who collaborate are better set for success in RISC-V than those who don’t. Thanks to an ecosystem coming together, the risk of RISC-V is reduced, and you can easily explore options when you are ready to make the shift. Codasip and Intel are exploring further possibilities for collaboration, and you will see more offerings going forward, always with quality and ease of use in mind.

Give it a try!

* © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. No product or component can be absolutely secure. 

Lauranne Choquin

Corporate Marketing Manager

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Codasip’s Expanding RISC-V Offering


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Watch as video

In the last three months, Codasip’s RISC-V processor offering has expanded considerably. For some years, Codasip has supplied Bk3 and Bk5 RISC-V cores aimed at low- to medium-complexity embedded applications. But recently four additional cores have joined the Codasip RISC-V offering.

Three of the cores, the SweRV Core™ EH1, EH2 and EL2, were designed by Western Digital and were open-sourced through CHIPS Alliance. These 32-bit cores are mainly aimed at high-performance embedded applications and complement the existing 32-bit Bk3 and Bk-5 cores. The EH1 offers outstanding embedded performance due to its superscalar, dual issue architecture. Even more performance is delivered by the EH2 which provides two hardware threads (harts). The EL2 core is more compact and is a single-issue core.

The RTL for all three SweRV Cores is available on GitHub free of license fees. However, RTL alone is not sufficient to use a SweRV Core in an SoC design. Firstly, a complete software toolchain is needed to allow embedded software to be developed. Secondly, a comprehensive EDA design flow needs to exist to undertake simulation, static analysis, and synthesis of the core’s RTL. It is important that the core can be easily integrated with peripherals, memories, and buses in order to implement a sub-system. EDA design flows need to keep up with revisions in both the processor IP and the EDA tools.

In December 2019, Western Digital and Codasip announced that they were cooperating to enable the deployment of open-source SweRV Cores in production silicon. Codasip’s SweRV Core Support Package (SSP) provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip, including but not limited to verification testbenches and intellectual property, reference scripts for leading EDA flows, models for simulation and emulation, and software development tools.

The Support Package is available in a Free version consisting of open-source components and mainly aimed at academic use, and in a Pro version aimed at commercial SoC design using commercial EDA tools. The SweRV Core Support Package for EH1 was released in April and support for EH2 and EL2 was added in June. In addition, Codasip offers services for customizing SweRV Cores.

Although the semiconductor industry regularly talks of comparing processor cores in terms of performance versus complexity or in terms of PPA (performance, power, area), both performance and complexity have different aspects. Many Systems-on-Chip (SoCs) use multiple cores and face different requirements for different functions. For example, a core for a subsystem such as Wi-Fi will have quite different needs to one running a feature-rich OS such as Linux.

The Codasip Bk7 RISC-V core, announced yesterday, is Codasip’s first application processor. Like all previous Bk core designs, it has been designed in the Codasip Studio processor design system. This means that its architecture can be readily modified to create application-specific processors.  It has all the features needed for running embedded Linux and will be the cornerstone for further application processor developments. The Bk7 core is a 64-bit core with a 7-stage pipeline and memory management unit (MMU). Future versions of the Bk7 will support symmetric and heterogenous multi-processing.

In future posts we will be looking into some of the different facets of processor performance and complexity in order to see how the expanded Codasip offering can be applied to varying applications. We will also provide more detailed information on the Bk7 processor core.

 

Roddy Urquhart

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What is SweRV Core EH2?


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In mid-May, CHIPS Alliance announced the open sourcing of the SweRV Core™ EH2 and SweRV Core EL2 designed by Western Digital. These cores, as well as the earlier EH1, are now supported by Codasip’s SweRV Core Support Package which provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip. But what is SweRV Core EH2?

The SweRV Core EH1 was the first to be released through CHIPS Alliance and was a core aimed at high-end embedded applications including Western Digital’s flash controllers and SSDs. The core is a dual issue, superscalar, high-performance core with 9 pipeline stages. The EH2 is an exciting further development aimed at delivering even more performance for IoT, artificial intelligence and data-intensive embedded applications.

The EH2 breaks new ground for RISC-V cores by being the world’s first dual threaded, commercial RISC-V core. Its 9-stage pipeline is based on that of the EH1, but it contains additional resources to support dual threading. There are doubled RISC-V general purpose registers, control and status registers, fetch buffers, instruction buffers, and other logic. By adding these incremental resources, the EH2 allows the host software to effectively ‘see two cores’. The simulated performance of the dual threaded EH2 core is an outstanding 6.3 CoreMark/MHz.

The SweRV Core EH2 supports machine mode only, meaning that it is aimed at applications using real-time operating systems or bare metal software. It has four 64-bit AXI4 bus interfaces for instruction fetch, load/stores, debug, and for accessing optional closely coupled memories. There is an optional instruction cache with either parity-based or ECC-based error protection, an optional instruction closely coupled memory (ICCM), and an optional data closely coupled memory (DCCM) which use ECC-based error protection.

The open-source RTL for the SweRV Core EH2 is available from CHIPS Alliance. However, considerably more than just RTL is needed to integrate the core into a system-on-chip (SoC) and to develop the associated firmware. A considerable amount of effort will be needed to create the EDA flows in particular and to maintain them over multiple RTL and EDA software versions.

The SweRV Core Support Package (SCSP) contains everything needed to deploy a Western Digital SweRV™ EH2 core in an integrated circuit, providing support for both EDA tool flows and embedded software development. SCSP saves the considerable effort that would be needed to set up EDA flows for the EH2 core from scratch. The SweRV Core Support Package for EH2 is available in both basic Free and Pro versions.

The Free version consists of open-source deliverables and infrastructure for using open-source EDA tools and an SDK. Users can access an internet forum for support.

The Pro version combines open-source and commercial deliverables. It provides flows, examples and models for using commercial EDA tools. This version includes professional support by e-mail and telephone.

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Vidtoo Technology Licenses Codasip’s Bk3 RISC‑V Processor for High‑Performance Computing SoC

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Vidtoo Technology Licenses Codasip’s Bk3 RISC‑V Processor for High‑Performance Computing SoC


December 17, 2018

Munich, Germany – December 17th 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, announced today that Vidtoo Technology, a leader in semiconductor products for machine learning and high-performance computing, has selected Codasip’s Bk3 processor for future HPC chips.

Vidtoo Technology, based in Hangzhou, China, focuses on high-bandwidth, high-performance, high-connectivity, artificial intelligence platforms and inference engines for data centers as well as 3D video processing technologies for industrial IoT applications and SR (Simulated Reality)/MR applications with on-chip decision making capabilities.

“We are pleased to announce our selection of Codasip’s Bk3 processor for our next HPC products. After careful consideration, we determined that Codasip offered the best combination of performance, value and design expansion ability. Those traits, plus best-in-class support and the broad ecosystem that the open RISC-V ISA brings, gave us confidence that Codasip was the right choice,” stated Thomas Hu, CEO of Vidtoo Technologies. “We look forward to a long and successful partnership with Codasip when we strive to provide customers with the optimal design across our product families.”

The Codasip Bk3 processor, based on the RISC-V open instruction set architecture (ISA) definition, features a single 3-stage in-order execution processor pipeline, and offers optional caches, IEEE 1149.1 debug, and industry standard bus interfaces. Further, the Bk3 – like all Codasip RISC-V implementations – is fully configurable and extensible, offering great advantage over traditional, fixed-configuration processor IP cores.

We are delighted that Vidtoo Technology has chosen Codasip to be its provider of RISC-V processor IP,” added Chris Jones, Codasip’s Vice President of Marketing. “Vidtoo is a rising star in the semiconductor industry with an impressive product portfolio that includes cutting-edge machine-learning devices. They have wide-ranging processing needs, and Codasip technology gives them a proven family of processor solutions complete with a comprehensive high-performance software toolchain.”

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information, visit www.riscv.org.

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Mythic Chooses Codasip to Deliver RISC-V Computing in their Revolutionary Neural Network Platform


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Campbell, California – December 10th 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, announced today that Mythic, a leader in artificial intelligence (AI) computing technology, has selected Codasip’s configurable Bk3 processor and Codasip Studio for future neural networking chips.

Mythic, based in Redwood City, California, and Austin, Texas, will deliver powerful, life-enhancing AI solutions that customers can push into anything, from fitness bands and hearing aids to self-driving cars and security cameras. The solutions are developed on a unique approach to neural network processing. The Mythic Intelligence Processing Unit (IPU), which performs the inference step of deep neural networks inside the same flash memory array which stores the neural network’s weights, delivers huge advantages in performance, cost, and power consumption versus alternative solutions.

“We chose Codasip’s Bk3 RISC-V processor and Codasip Studio for our PCIe-attached IPU deep learning accelerator because it gave us the flexibility to create a truly unique processor that was specific to our needs, while maintaining compliance to the RISC-V standard,” stated Ty Garibay, VP of Hardware Engineering at Mythic. “While we have the expertise to build our own RISC-V processor, we determined that Codasip Studio, with its automatic generation of both verified hardware and fully compatible software toolchain, was a more efficient approach and allowed us to focus on other critical areas of the product development.”

The Codasip Bk3 processor, based on the RISC-V open instruction set architecture (ISA) definition, features a single 3-stage in-order execution processor pipeline and offers optional caches, IEEE 1149.1 debug, branch prediction, and industry standard bus interfaces. Further, the Bk3 – like all Codasip RISC-V implementations – is fully configurable and extensible, offering great advantage over traditional, fixed-configuration processor IP cores.

With Codasip Studio, designers can begin with a high-level description of a RISC-V micro-architectural implementation defined and delivered by Codasip, and then describe their desired architectural and ISA modifications in the CodAL architecture description language, and then automatically synthesize the design’s RTL, testbench, virtual platform models and processor SDK (C/C++ compiler, debugger, profiler, and other parts).  Time that would otherwise be required to maintain a complete SDK and implementation is significantly reduced thanks to the methodology that uses an Instruction Accurate (IA) processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.

We welcome Mythic to the growing roster of customers that are partnering with Codasip to deliver innovative products based on the RISC-V architecture,” stated Chris Jones, Codasip’s Vice President of Marketing. “RISC-V is ideal for machine learning applications, and Mythic will deliver revolutionary products that employ highly optimized Codasip RISC-V cores.”

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

About Mythic

Mythic is accelerating AI that works for everyone. Today, it is difficult, time-consuming and expensive to build and deploy reliable AI. By offering mixed-signal chips with revolutionary power, cost, and performance capabilities, along with easy-to-use software tools, Mythic is removing those limitations and empowering every AI developer. Mythic’s focus is simple: to enable the next great wave of AI innovation.

Mythic is supported by leading venture capital investors including Softbank, DFJ, Lux, and Data Collective. The company has offices in Austin, TX, and Redwood City, CA.  For more information about Mythic, visit www.mythic-ai.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information, visit www.riscv.org.

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Codasip Secures $10M in Series A Financing to Expand RISC-V Processor Technology Offerings


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Munich, Germany – December 4th, 2018 – Codasip GmbH, the leading supplier of RISC-V® embedded processor IP, announced today that it has raised $10M in a Series A investment round led by private equity firms Ventech Capital of Paris, France, Shenzhen Capital Group Co., Ltd. of Shenzhen, China, Paua Ventures of Berlin, Germany, and strategic investor Western Digital, following the initial investment led by Credo Ventures of Prague, Czech Republic.

This investment will allow Codasip to grow its global sales and support team while expanding its product development efforts to bring best-in-class RISC-V processor intellectual property and optimization tools to customers around the world.

“The RISC-V movement is growing at a rapid pace and transitioning from an era of raising awareness to an era of customer adoption,” stated Christian Claussen, General Partner of Ventech Capital and a board member of Codasip. “Codasip have the tools and expertise developed over the last decade to create a broad portfolio of licensable RISC-V processors and bring them to market. Ventech Capital is confident that Codasip will continue to provide innovative products to the semiconductor industry.”

Martin Fink, Chief Technology Officer at Western Digital, added: “Western Digital is focused on the next generation of innovation to enable new classes of applications like machine learning, AI, and analytics to deliver the possibilities of data. RISC-V offers a platform for innovation unshackled from the proprietary interface of the past, and this freedom allows us to optimize special-purpose computing capabilities targeted at big data and fast data applications.”

Karel Masařík, Codasip’s founder and CEO, said: “We are honored to welcome aboard this global syndicate of investors who share Codasip’s vision of bringing innovative RISC-V-based processors and optimization tools to the world, and we appreciate the continued dedication, commitment, and support of our earlier investors and the current team.

Codasip aims to have the most comprehensive portfolio of RISC-V processor technology in the industry. Codasip Studio allows for rapid processor development and helps customers differentiate their products through processor IP that is tailored to their design and software requirements, and does so with less cost and risk than using general-purpose offerings. Studio dramatically simplifies the process of optimizing a processor, delivers enormous performance improvement to customers, and allows them to build their own unique RISC-V core that is just right for their application.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 with research and development located in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. Codasip is currently venture-backed by Credo Ventures, Ventech Capital, Shenzhen Capital Group Co., Ltd. of Shenzhen, China, Paua Ventures, and Western Digital.

For more information about Codasip’s products and services, visit codasip.com.

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. For more information, visit www.riscv.org.

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Codasip Expands its Global Reach by Signing Channel Partnerships throughout Asia


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Campbell, California – September 10th 2018 – Codasip, the leading supplier of RISC‑V® embedded processor IP, today announced that it has signed new reseller representative agreements with leading firms in China, Taiwan, Japan, and India.

New strategic partnerships were formed with Shanghai Jiatao, Maojet Technologies of Taiwan, Delphinium Technologies of Bengaluru, India, and Japan Marketing Office to assist Codasip in reaching the rapidly expanding Asia markets.

“Adding these great companies to our partner roster demonstrates our commitment to making Codasip the premier provider of RISC-V processors,” stated Karel Masařík, founder and CEO of Codasip. “RISC-V momentum is growing and we are uniquely positioned for success with a global presence and a strategy of delivering configurable RISC‑V-based products and development tools.”

Codasip aims to have the most comprehensive portfolio of RISC‑V processor IP in the industry, which is achieved by employing the Codasip Studio processor development tools to continually bring new cores to market. The unique toolset also helps customers differentiate their products by automatically tailoring their processor IP to design and software requirements – and it does so with less cost and risk than with using general-purpose components.

Studio dramatically simplifies the process of tailoring a processor solution and delivering potentially enormous performance improvements.  Further, end users can exploit the power of Studio themselves to build their own unique RISC-V processor that is just right for their application.

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
For more information, visit www.riscv.org.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

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Codasip Inks Deal with Delphinium Technologies to Establish India Presence


September 10, 2018

Campbell, California – September 10th 2018 – Codasip, the leading supplier of RISC‑V® embedded processor IP, today announced that it has signed a representative agreement with Delphinium Technologies to establish Codasip’s presence in India.

Delphinium Technologies of Bengaluru, India, is focused on bringing state-of-the-art EDA technologies and IP to the electronics engineering world.

“Indian companies, government-backed research facilities and universities are all heavily invested in the RISC‑V movement,” stated Susheel Kumar, founder and director of Delphinium.  “Codasip’s technology can help these enterprises become more productive as they develop innovative RISC‑V derivatives. We look forward to helping Codasip introduce their RISC-V processors, tools, and design methodology to the India design community.”

India represents a new frontier for processor IP companies like Codasip,” stated Jerry Ardizzone, Vice President of Worldwide Sales at Codasip. “We are uniquely positioned with our configurable RISC‑V-based products and development tools to help jumpstart the growing India processor and semiconductor design communities, and we look to Delphinium to help us establish roots in the market there.”

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
For more information, visit www.riscv.org.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.
For more information about Codasip’s products and services, visit codasip.com.

About Delphinium

For more information about Delphinium, visit www.delphiniumtech.com.

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Maojet and Codasip Join Forces to Deliver RISC-V Processors to Taiwan


September 10, 2018

Campbell, California – September 10th 2018 – Codasip, the leading supplier of RISC‑V® embedded processor IP, today announced that it has signed a representative agreement with Maojet Technology Corporation, making them Codasip’s exclusive sales partner in Taiwan.

Maojet is the leading EDA tool and IP distributor in Taiwan, established in 1992 and having since built a comprehensive portfolio of EDA tools from system level to RTL, manufacturing and PCB, in addition to a large family of silicon-proven SoC IP solutions.

“We are witnessing growing RISC-V momentum in Taiwan, as our customers are always looking for new and innovative IP,” said Ted Tsai, General Manager of Maojet.  “The combination of Codasip’s RISC‑V processors and processor development tools is unique to the industry, and exactly what our customers need to differentiate in the highly competitive semiconductor market. We anticipate a long and successful partnership with Codasip.”

Taiwan is home to some of the world’s most innovative semiconductor companies and represents a huge opportunity for Codasip technology,” stated Jerry Ardizzone, Vice President of Worldwide Sales at Codasip. “Together, Maojet and Codasip will work to bring the best in RISC‑V technology to these companies and support them in reaching their fullest potential.”

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
For more information, visit www.riscv.org.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.
For more information about Codasip’s products and services, visit codasip.com.

About Maojet

For more information about Maojet, visit www.maojet.com.tw.

Kava

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