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Codasip Releases Studio 8, a Breakthrough in RISC-V Automation, and the Bk7 RISC-V Processor Core for Real-Time Computing Applications


December 6, 2018

Munich, Germany – December 6th, 2018 – CodasipGmbH, the leading supplier of RISC-V® embedded processor IP, announced today the latest version of Studio, a suite of tools optimized for the development and verification of RISC-V processors, and the Bk7 processor, the first Codasip RISC-V core optimized for Linux and real-time performance.

“As the RISC-V ISA specification evolves and adds an ever-increasing number of optional architecture extensions, a processor design methodology that allows for both rapid architectural exploration and simplified creation of easily implementable RTL becomes essential,” stated Chris Jones, Vice President of Marketing at Codasip. “What is needed is a high-level processor description language optimized for RISC-V, so Codasip has delivered Studio 8, a comprehensive tools suite for RISC-V processor development.”

With Studio, designers write a high-level description of a processor in CodAL, an architecture description language, and then automatically synthesize the design’s RTL, test bench, virtual platform models, and processor SDK (C/C++ compiler, debugger, profiler, etc.). Time that would otherwise be required to maintain a complete SDK and implementation is significantly reduced thanks to the methodology that uses an Instruction Accurate (IA) processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.

Codasip employs this silicon-proven methodology to create and deliver a broad portfolio of licensable RISC-V processor IP.  Through these product developments, Studio has evolved to make it more suitable for implementing and extending the instruction set of RISC-V cores. The 8th generation of Codasip Studio, just announced, adds significant new functionality and features, making it the most advanced and effective technology on the market for tailoring RISC-V processors to meet chip designers’ application-specific needs. Specifically, Studio 8 includes:

  • Support for LLVM debugger (LLDB) and OpenOCD,
  • LLVM 7.0,
  • Studio/CodeSpace IDEs based on Eclipse Oxygen along with more interactive consoles,
  • improved test suites and verification to better support user-defined RISC-V extensions.

Further, Codasip architects employed Studio to develop the Bk7 processor, the latest RISC-V micro-architecture in the Codasip portfolio.

A 64-bit machine featuring a balanced 7-stage pipeline with branch prediction, optional full MMU with virtual addressing support for operating systems such as Linux, and support for the popular RISC-V standard extensions as well as industry-standard external interfaces, the Bk7 is Codasip’s highest-performance processor to date and is ideal for system-on-chip designers who need the right balance of power and performance.  Also, the Bk7 is fully customizable so architects can easily add additional instructions, registers or interfaces. And as with each member of the Codasip Bk processor family, the Bk7 comes with the following deliverables:

  • Readable Verilog or VHDL RTL along with test benches and synthesis scripts,
  • SDK consisting of LLVM-based compiler, advanced profiling and debugging tools,
  • both cycle-accurate and fast instruction-accurate simulation tools.

Studio 8 and the Bk7 processor are generally available in the first quarter of 2019, with early access to selected customers immediately.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 with research and development located in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. Codasip is currently venture-backed by Credo Ventures, Ventech Capital, Shenzhen Capital, Paua Ventures, and Western Digital.

For more information about Codasip’s products and services, visit codasip.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open-standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information about RISC-V, visit www.riscv.org.[/cs_text][/cs_column][/cs_row][/cs_section][/cs_content]

Kava

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Codasip Announces Studio 7, Design and Productivity Tools for Rapid Generation of RISC-V Processors


January 23, 2018

Brno, Czech Republic – January 23rd, 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, today announced that it has launched the 7th generation of its Studio, the unique IP-design and customization software that allows for fast configuration and optimization of RISC-V processors, customer-proprietary processor architectures, and their accompanying software development toolchains.

Studio 7 adds significant new functionality and features, making it the most advanced and effective technology on the market for tailoring RISC-V processors to meet chip designers’ application-specific needs. Codasip engineers have used the Studio design flow to create the broadest portfolio of RISC-V processors in the industry, and they now put the power in the hands of customers to further customize and extend the RISC-V instruction set, based on the unique requirements of the algorithms being run.

Studio can be used for:

  • processor prototyping for a specific application domain,
  • fast design space exploration,
  • development of custom extensions using Codasip’s architecture description CodAL language.

Studio then generates hardware and corresponding SDKs that are aware of the custom extensions, including

  • Verilog or VHDL RTL and System Verilog UVM environments,
  • testbenches and synthesis scripts,
  • full compiler toolchain including advanced profiling and debugging tools,
  • both cycle-accurate and fast instruction-accurate simulation tools.

Some of the new features included with Studio 7:

  • Native support for industry-standard AMBA interfaces, allowing for easy replacement of other processor cores while reusing your existing, proven peripheral IP.
  • IEEE 1149-7-compatible 2-wire JTAG to minimize pin-count.
  • Improvements in clock-gating for low-power requirements.
  • Major updates to Codespace, the optional Eclipse-based IDE, and the underlying software tools, including support for LLVM 5.0.

“Studio 7 is a big step forward for Codasip’s advanced processor creation technology, and will take the guesswork out of implementing the ever-expanding number of ISA options in the RISC-V specification. Studio can help generate processors well-suited to the widest range of application areas, from machine learning inference engines to host processor DSP offload, networking, and storage,” stated Karel Masařík, CEO and co-founder of Codasip. “With Studio 7, there is no need to settle for a one-size-fits-all processor.”

The Studio 7 processor design and customization tool suite is available now.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information about RISC-V, visit www.riscv.org.[/cs_text][cs_text]

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

Kava

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Codasip Announces Bk5-64, a New 64-bit RISC-V Processor


November 28, 2017

Brno, Czech Republic – November 28th, 2017 – Codasip, the leading supplier of RISC-V® embedded processor IP, today announced that it has expanded its Berkelium processor portfolio to include the Bk5-64, its first implementation of the 64-bit RISC-V ISA.

Codasip now offers customers the broadest selection of RISC-V processors in the market, spanning from the ultra-low-power zero-stage Bk1 to the high-data-bandwidth, energy-efficient Bk5-64. All Berkelium processors are generated via the unique Codasip Studio customization tool, allowing for fast configuration and optimization of the cores.

With the rapid expansion of data-intensive applications such as storage and wireless networking, the market is asking for embedded processor solutions with the right balance of performance and energy efficiency that 64-bit computing requires,” stated Karel Masařík, founder and CEO of Codasip. “By introducing the Bk5-64, Codasip is addressing the need for affordable 64-bit embedded processors, complete with a state-of-the-art LLVM-based software development toolchain with advanced profiling.”

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

Said Rick O’Connor, Executive Director of the non-profit RISC-V Foundation, “Today’s announcement from Codasip shows continued growth of the RISC-V architecture and the industry’s need for a new open, free ISA. We look forward to seeing more developments from Codasip and others from the RISC-V ecosystem in the future.

The Berkelium Bk5-64 RISC-V processor is available later in Q4 of 2017.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

Kava

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Codasip Announces Latest RISC-V Processor


August 21, 2017

The Newest Codasip RISC-V Processor is Ideal for IoT Designs

Brno, Czech Republic – August 21st 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced the newest addition to their Berkelium (Bk) family of RISC-V processors. The Codasip Bk-1 processor is an FSM processor targeted at the Internet of Things (IoT) by offering ultra-low power, the lowest cost of all comparable embedded processors, and optimal performance/power efficiency.

Karel Masařík, CEO and founder of Codasip, stated: “This processor is perfect for IoT ASIC designers looking to move up from 8-bit processors to 32-bit processors. Like all members of the Codasip Bk family of processors, the Bk-1 is fully compliant with the RISC-V open standard, assuring customers that their embedded software is truly portable and their designs are not locked into a proprietary instruction set architecture (ISA) such as Arm.”

The Bk-1 processor was designed to provide impressive 32-bit performance, small code size, and minimal power, area, and cost. In its basic configuration, the Bk-1 starts at 9k gates while delivering a maximum clock frequency of up to 350 MHz in a 55nm process. The Bk-1 has an optional power management unit, JTAG debug controller, and bridges to the AMBA buses so it can be easily integrated into existing Arm designs.

Codasip provides their customers with high-level design tools that automatically profile the embedded SW and allow ASIC designers to tailor the Bk-1 processor exactly to its intended application. This unique ability to automatically modify the Codasip cores results in far better implementations compared to other processor IP vendors, and allows for the process to be easily completed in a day or two with the silicon proven Codasip Studio tool suite.

“Codasip’s new Bk-1 processor is another great milestone for the RISC-V ecosystem and shows ongoing market growth of its open and free architecture,” said Rick O’Connor, executive director of the non-profit RISC-V Foundation. “The Foundation will continue to support member organizations, such as Codasip, in bringing to market RISC-V-based processors that enable new designs and innovation.”

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of an open standard, such as the RISC-V ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V foundation (riscv.org) and a long-term supplier of LLVM and GNU based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. More information on Codasip’s products and services is available at codasip.com.

Press Contact

Codasip North America
Dan Ganousis
ganousis@codasip.com
+1 (303) 859-3048

Codasip EMEA
Roddy Urquhart
urquhart@codasip.com
+44 753 158 7023

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Codasip announces availability of Codasip Studio 6.0


June 3, 2016

The major theme for the 6.0 release has been scalability and the ability to create and reuse ASIP projects in a hierarchal manner. In addition there are significant small enhancements and bug fixes across every aspect of the tools.

For a full changelog, please see the download section.

Kava

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Codasip Releases Studio 8, a Breakthrough in RISC-V Automation, and the Bk7 RISC-V Processor Core for Real-Time Computing Applications

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