Using processor design automation
to customize RISC-V Processors
In customizing a RISC-V core to a particular computational workload, it is essential to be able to experiment with new custom instructions and to rapidly get feedback on the efficiency of the design. If the core is described in an architectural language, design exploration can be enabled by a processor design automation tool.
All Codasip RISC-V cores are designed using our unique CodAL architecture description language. The processor description in CodAL is developed using Codasip Studio. If you license the CodAL description of a Codasip core, you can use Studio to profile application software, to experiment with RISC-V custom instructions. Studio generates an LLVM software toolchain for the customized core. It also generates RTL, test benches, and a UVM verification environment.