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What’s new in Codasip

Learn more about Codasip, our products, RISC-V, industry news, and more.

23 May 2023Processors

No one-size-fits-all approach to RISC-V processor optimization

16 May 2023Industry

Shifting left for success: Highlights from the Siemens EDA User 2 User conference

08 May 2023RISC-V

5 reasons why you should attend the 2023 RISC-V Summit Europe in Barcelona

02 May 2023Processors

RISC-V customization, HW/SW co-optimization, and custom compute

25 Apr 2023Codasip Studio

Working with the NimbleAI project to push the boundaries of neuromorphic vision

04 Apr 2023RISC-V

Raising RISC-V processor quality with formal verification

21 Mar 2023Industry

Embedded World 2023: it’s time to architect all ambitions with custom compute

25 Jan 2023Industry

Highlights from 2022, a turning year for Codasip

22 Dec 2022RISC-V

5 things I will remember from the 2022 RISC-V Summit

21 Nov 2022University Program

Being a design verification engineer is fun and rewarding

17 Nov 2022RISC-V

How to reduce the risk when making the shift to RISC-V

22 Sep 2022RISC-V

5 good things about RISC-V

12 Sep 2022RISC-V

Collaboration leading the way for broad RISC-V adoption

05 Sep 2022Codasip Studio

Codasip Studio 9.2.0: what’s new?

29 Aug 2022Processors

Creating specialized architectures with design automation

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