Resources

Papers and
case studies

What’s new at Codasip

Read our papers and case studies for insights, reports, and other deep dives.

14 Aug 2023papers

Re-targetable C/C++ LLVM compiler for RISC-V – Poster

31 Jul 2023papers

Effortless DSP extensions design for embedded RISC-V CPUs – Poster

19 Jul 2023papers

FIR and Median Filter accelerators in CodAL – Technical paper

27 Jun 2023papers

Compact CORDIC accelerator implementation for embedded RISC-V core – Poster

27 Jun 2023papers

RISC-V as an enabler of heterogeneous compute – Poster

27 Jun 2023papers

Unlocking the potential of RISC-V with HW/SW co-design – Poster

04 Apr 2023papers

A formal-based approach for efficient RISC-V processor verification

29 Mar 2023papers

Fast Fourier Transform (FFT) Accelerator in CodAL

21 Nov 2022papers

Extending RISC-V processors in the field with Codasip Studio & Menta eFPGA

17 Nov 2022papers

Efficient verification of RISC-V processors – Technical paper

14 Sep 2022papers

Compact NN accelerator in CodAL – Technical paper

12 Sep 2022papers

Compact neural network accelerator in CodAL – Case study

30 Aug 2022papers

Neural networks empowered by custom instructions – Case study

30 Aug 2022papers

Microsemi – Case study

29 Jul 2022papers

Semiconductor scaling is failing – Technical paper

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