Jump-start with an existing design
Customizing an existing design is the most convenient way to your custom processor core, tailored for the intended domain. Our smart technology with highly automated workflow guarantees fast results with minimal manual effort.
RISC-V is an open ISA (Instruction Set Architecture) that has been created with customization in mind, and is therefore ideal for the job.
The RISC-V instruction set has three classes of instruction: There is a base instruction set for a given wordlength (32-, 64- or 128-bit), different groups of optional standard extensions and non-standard custom extensions.
There is a large part of the opcode space which is available for custom extensions. A processor architect can use such extensions to deliver extra processing performance to address a given computational workload.
How to Customize
Using the Power of RISC-V
Tool for the job
Codasip Studio is a market-unique suite of tools for automating the design of programmable cores using the CodAL architecture description language. The technology is particularly synergistic with the RISC-V ISA (although it can be applied to cores based on any other ISA too). It provides two approaches to implementing the custom instructions in hardware:
- Implementing the logic in the processor pipeline,
- Connecting a co-processor with a generated interface.
Some processor IP vendors, too, offer tools and extensible cores which allow a limited amount of customization. However, Codasip Studio offers far more freedom, both in terms of ISA and microarchitecture.
How others do it
How we do it
Codasip offers off-the-shelf RISC-V processor cores which are licensed in the usual way with RTL, a testbench and SDK. These cores can also be licensed in the CodAL source code which was used to design the cores and to generate the SDK and HDK. The CodAL source can be edited to create custom extensions and to modify other architectural features.
Microsemi used Codasip Studio on an audio design where they were seeking to replace a proprietary embedded core with a RISC-V one. They started with the base 32-bit instruction set but found that the cycle count was far too high. Adding the multiplication instructions improved performance but did not achieve their requirements. Finally, they worked with Codasip to create custom DSP extensions that significantly improved the performance 56× with processor core gatecount growing by 2.4×.
Not only did they achieve their performance goal but their codesize reduced from 232 kB to 64 kB reducing the required instruction memory area by 3.6×.
The Microsemi case: Reducing cycle count with custom RISC-V extensions. Source: Codasip.