RISC-V Processor Customization
One approach to creating application-specific processors is to take an existing core and to customize it. Working this way is efficient both in terms of design effort and time to market. Historically, many popular commercial architectures had fixed architectures. RISC-V’s open and modular instruction set makes it significantly easier to customize existing RISC-V cores. Another key enabler is to describe the RISC-V core in a processor description language allowing the RTL, verification environment, and software toolchain to be automatically generated.
Processor optimization requires customization
For many general purposes, a standard RISC-V product is a good fit. However, if you need optimal features and PPA for a certain workload, modifying an existing design is the most convenient way to create a processor tailored for its task. Codasip gives you the ability to freely customize a standard Codasip processor by modifying both the microarchitecture and the instruction set with Codasip Studio, our complete end-to-end architecture customization solution.
Tuning designs to different workloads
Codasip RISC-V cores have been customized in a number of applications including artificial intelligence, wireless and audio processing.
Using processor design automation to customize RISC-V processors
In customizing a RISC-V core to a particular computational workload, it is essential to be able to experiment with new custom instructions and to rapidly get feedback on the efficiency of the design. If the core is described in an architectural language, design exploration can be enabled by a processor design automation tool.
All Codasip RISC-V cores are designed using our unique CodAL architecture description language. The processor description in CodAL is developed using Codasip Studio. If you license the CodAL description of a Codasip core, you can use Studio to profile application software, to experiment with RISC-V custom instructions. Studio generates an LLVM software toolchain for the customized core. It also generates RTL, testbenches, and a UVM verification environment.