Blog
Learn more about Codasip, our products, RISC-V, industry news, and more.
03 Oct 2023Processors
Formal verification best practices: towards end-to-end properties
26 Sep 2023Processors
Formal verification best practices: investigating a deadlock
21 Sep 2023Industry
Saving the planet, one byte at a time
19 Sep 2023Processors
Formal verification best practices to reach your targets
12 Sep 2023Codasip Studio
Configurable LLDB for (not only) embedded RISC-V processors
31 Aug 2023Codasip Studio
How the SYCLOPS project democratizes AI acceleration
01 Aug 2023Processors
What you should ask for instead of just PPA
01 Aug 2023Processors
Why you should stop asking for PPA
25 Jul 2023Codasip Studio
Re-targetable LLVM C/C++ compiler for RISC-V
Press releases
Check out the latest news about Codasip, the industry, and more.
26 Sep 2023press release
Codasip selects Verilock to provide secure hardware authentication technology
05 Sep 2023press release
Codasip collaborates with Siemens to deliver trace solution for custom processors
06 Jul 2023press release
Codasip welcomes Axel Strotbek as new chairman of the board
22 Jun 2023press release
Codasip partners with SmartDV to accelerate chip design projects
14 Mar 2023press release
Codasip and IAR demonstrate dual-core lockstep for RISC-V
15 Feb 2023press release
embedded world 2023: Codasip presents on custom compute and RISC-V design
15 Dec 2022press release
Codasip Lead IP Architect chosen for the RISC-V Contributor Award
12 Dec 2022press release
Codasip launches SecuRISC5 initiative
07 Dec 2022press release
Codasip launches Codasip Labs to accelerate advanced technologies
01 Dec 2022press release
Codasip and Intel bring RISC-V development to higher-education
Technical papers and case studies
Read our papers and case studies for insights, reports, and other deep dives.
14 Aug 2023papers
Re-targetable C/C++ LLVM compiler for RISC-V – Poster
31 Jul 2023papers
Effortless DSP extensions design for embedded RISC-V CPUs – Poster
19 Jul 2023papers
FIR and Median Filter accelerators in CodAL – Technical paper
27 Jun 2023papers
RISC-V as an enabler of heterogeneous compute – Poster
27 Jun 2023papers
Unlocking the potential of RISC-V with HW/SW co-design – Poster
04 Apr 2023papers
A formal-based approach for efficient RISC-V processor verification
29 Mar 2023papers
Fast Fourier Transform (FFT) Accelerator in CodAL
17 Nov 2022papers
Efficient verification of RISC-V processors – Technical paper
Events
Check out the industry events we are planning to attend in the months ahead. Come and meet us – whether that’s in person, or virtually.
10/11/2023Guangzhou, China
ICCAD China
18/10/2023Munich, DE
Samsung Foundry Forum EMEA
14/11/2023Munich, DE
DVCon Europe
23/10/2023Online
Codasip and Siemens webinar
12/10/2023Crete - GR
Career Fair ‘Meet the companies’
07/11/2023Santa Clara, US
RISC-V Summit US 2023
Videos
From demos to interviews and conference talks, learn more about our technology, custom compute offer, people, and more.