SEGGER and Codasip Announce Cooperation on RISC-V
Press Release by Roddy Urquhart, June 22, 2021.
SEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE fully support Codasip’s RISC-V processors, right out-of-the-box.
SEGGER’s J-Link debug probe supports RISC-V debug on Codasip’s processor cores. Furthermore, J-Link, using the Open Flashloader concept, allows programming of flash memories connected to devices using Codasip RISC-V cores, while Embedded Studio’s Linker and Runtime Libraries are perfect for minimizing code size.
“Having SEGGER’s J-Link and Embedded Studio fully support our RISC-V cores represents excellent added value for our ecosystem,” says Roddy Urquhart, Sr. Marketing Director at Codasip.
“As a member of the RISC-V foundation, we are excited to further contribute to the ecosystem by supporting Codasip,” says Ivo Geilenbruegge, Managing Director of SEGGER. “SEGGER is highly engaged in the RISC-V market and started offering software libraries and tools early on. We are excited to continue our collaboration with Codasip.”
Codasip's family of 32-bit embedded processors (names beginning with "L") and 64-bit embedded processors (names beginning with "H") are based on the RISC-V Instruction Set Architecture (ISA) and can be customized to meet domain-specific requirements.
What's New in Codasip

05/16/22
Blog
by Rupert Baines
Design for differentiation: architecture licenses in RISC‑V

05/10/22
Press Release
by David Marsden
Codasip appoints SH Lee to deliver RISC-V innovations to Korean OEMs

05/05/22
Blog
by Jamie Broome
Building the highway to automotive innovation

05/03/22
Press Release
by David Marsden
Codasip adopts Siemens’ OneSpin tools for formal verification

05/02/22
Blog
by Keith Graham
Processor architecture optimization is not a barrier for university researchers

04/29/22
Blog
by Philippe Luc
Building a Swiss cheese model approach for processor verification

04/21/22
Press Release
by David Marsden
Codasip appoints Jamie Broome as its Automotive VP

04/08/22
Whitepaper
by Roddy Urquhart
Semiconductor Scaling is Failing

04/06/22
Press Release
by David Marsden
Codasip appoints Japan EDA veteran

04/04/22
Blog
by Philippe Luc
Measuring the complexity of processor bugs to improve testbench quality

03/24/22
Blog
by Roddy Urquhart
Closing the Gap in SoC Open Standards with RISC-V

03/16/22
Blog
by Lauranne Choquin
How Today’s Engineering Students Will Become the Processor Engineers of Tomorrow