SEGGER and Codasip Announce Cooperation on RISC-V

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Featured image by courtesy of SEGGER. Post published in 
Press Releases
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Press Release
Monheim am Rhein & Munich, Germany
June 22, 2021

SEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE fully support Codasip’s RISC-V processors, right out-of-the-box.

SEGGER’s J-Link debug probe supports RISC-V debug on Codasip’s processor cores. Furthermore, J-Link, using the Open Flashloader concept, allows programming of flash memories connected to devices using Codasip RISC-V cores, while Embedded Studio’s Linker and Runtime Libraries are perfect for minimizing code size.

“Having SEGGER’s J-Link and Embedded Studio fully support our RISC-V cores represents excellent added value for our ecosystem,” says Roddy Urquhart, Sr. Marketing Director at Codasip.

“As a member of the RISC-V foundation, we are excited to further contribute to the ecosystem by supporting Codasip,” says Ivo Geilenbruegge, Managing Director of SEGGER. “SEGGER is highly engaged in the RISC-V market and started offering software libraries and tools early on. We are excited to continue our collaboration with Codasip.”

Codasip's family of 32-bit embedded processors (names beginning with "L") and 64-bit embedded processors (names beginning with "H") are based on the RISC-V Instruction Set Architecture (ISA) and can be customized to meet domain-specific requirements.

Media Contacts
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Roddy Urquhart
Sr. Marketing Director
Codasip Group
Dirk Akemann
Marketing Manager
SEGGER
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