Codasip RISC‑V Processors

Codasip Processor Cores

Our processor cores are built on RISC-V, a modern open Instruction Set Architecture (ISA) and implemented in Codasip Studio. This means that they are offered either using a conventional licensing model as RTL, testbenches and SDK, or by licensing the CodAL code used to create the core. If you license the CodAL, you can use the core as a quick starting point for your own custom design using our unique Codasip Studio toolset.

The RISC-V instruction set with custom DSP extensions delivers the performance we require while keeping silicon area to a minimum. The best-in-class Codasip Studio development tools enable us to profile our software and find an optimal set of instructions for our application.

Jin Park, CTO, Dongwoon Anatech

Codasip RISC‑V Processors at a Glance

Codasip offers three processor families:

  • Small and energy-efficient Low Power Embedded cores
  • More powerful High Performance Embedded cores
  • Most advanced Application cores able to run Linux

In each of the families, you can choose from a number of series based on the microarchitecture complexity.

All the cores are fully customizable and adaptable to the unique needs of your project.


Choose your Codasip RISC‑V Processor

F = Floating Point Unit, P = RISC-V P Packed SIMD Extension, MP = Multiprocessing
*Not recommended for new designs.

All Cores

  • Standard RISC-V debug
  • JTAG (4pin/2pin)
  • Compressed instructions
  • AMBA buses

Low Power Embedded

  • 32-bit
  • Up to 128 interrupts

High Performance Embedded

  • 64-bit
  • Up to 256 interrupts


  • 64-bit
  • Floating point unit
  • Linux support:
    • RV64GC ISA
    • Atomic instructions
    • Supervisor mode
    • MMU
  • Multicore options
  • Dual-issue options
  • 7-stage pipeline
  • IMC instruction set
  • 32 registers
  • Branch predictor
  • Parallel multiplier

Codasip A70
Codasip A70P
Codasip A70-MP
Codasip A70P-MP

  • 5-stage pipeline
  • IMC instruction set
  • 32 registers
  • Branch predictor
  • Parallel multiplier

Codasip L50
Codasip L50F

Codasip H50
Codasip H50F

  • 3-stage pipeline
  • IMC instruction set
  • 32 registers
  • Parallel multiplier

Codasip L31
Codasip L31F

Codasip L30*
Codasip L30F*

  • 3-stage pipeline
  • EMC instruction set
  • 16 registers
  • Sequential multiplier
Codasip L11
Codasip L10*

Choose your Codasip RISC-V Processor

Click the image to enlarge

Codasip RISC-V processors product table

FPGA Evaluation Platform

If you would like to evaluate a single Codasip RISC-V core, you can use Codasip's FPGA evaluation platform. Codasip will supply you with an eval kit consisting of an FPGA bitstream, SDK and the CodeSpace IDE, along with a step-by-step quick start guide. You should be up and running with your first C program in 15 minutes.

Please note that obtaining the package is subject to signing an Evaluation Agreement. You are welcome to contact us for more details.

The Codasip Embedded Processor Evaluation Platform based on AHB targets the cost-effective Digilent Nexys A7 FPGA board and is suitable for low-power and high-performance embedded cores such as the Codasip L11, L31, L50, and H50. It can be used for evaluating systems with either bare metal software or RTOS (e.g. FreeRTOS).

I want a Codasip RISC‑V Processor

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