Capability Hardware Enhanced RISC Instructions
As defined by the University of Cambridge, CHERI extends conventional hardware Instruction-Set Architectures (ISAs) with new architectural features to enable fine-grained memory protection and highly scalable software compartmentalization.
Increasing processor securitywith Custom Compute
*CVE stands for Common Vulnerability and Exposure as defined and explained here.
The first commercial implementation of CHERI technology
The real-life solution to protect your end users
The Codasip 700 family includes security enhanced processors with CHERI.
Bringing security to everyonewith Custom Compute
Privacy violation, reputational damage, financial loss, or even threat to human lives from an unsafe and unsecure product are not acceptable, be it IIoT, automotive, aerospace, or any other consumer product.
Using Codasip Studio, we have added built-in, fine-grained memory protection by extending the RISC-V ISA with CHERI-based custom instructions. To enable the use of these instructions, we are also delivering the software environment to take advantage of CHERI technology, bringing a full software development flow to add memory protection.