DAC 2024 – Showcasing the future of RISC-V through EDA
by Brett Cline As I sat on the plane in Boston it’s fair to say that I was curious about what DAC 2024 would bring. The previous year was much better than I expected but a cold June in San Francisco wasn’t exactly what I was dreaming about. Afterall, while I was heading to San […]
Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in Munich
by Tora Fridholm This week, the 2024 edition of RISC-V Summit Europe took place in lovely Munich, Germany. Those of us who attended last year’s edition in Barcelona might not have expected the same weather but Munich was up for the challenge and served us a sunny, hot week, only interrupted by a thunderstorm that […]
Collaboration leading the way for broad RISC-V adoption
We recently announced a partnership with Intel as part of the launch of the Intel® Pathfinder for RISC-V, making leading RISC-V technology more accessible for prototyping, production design or research purposes using Intel FPGAs. Intel Pathfinder for RISC-V allows for a variety of RISC-V cores and other IP to be instantiated on FPGA platforms, with the ability to […]
Codasip Studio 9.2.0: what’s new?
Codasip Studio in its 9.2.0 release is now available. This new version of our unique processor design automation toolset comes with a series of new features that both expand and optimize its applications. The new features supported in Codasip Studio 9.2.0 include: Macro Processor. Arrays in CodAL. uRISC-V 2.0. Pipeline definition in modules. Simulator Save state and […]
A Codasip Greece Design Center to extend leadership in Europe
In conversation with Giorgos Nikiforos, Director of the Codasip Greece Design Center
Codasip’s Expanding RISC-V Offering
In the last three months, Codasip’s RISC-V processor offering has expanded considerably. For some years, Codasip has supplied Bk3 and Bk5 RISC-V cores aimed at low- to medium-complexity embedded applications. But recently four additional cores have joined the Codasip RISC-V offering.
What is SweRV Core EH2?
In mid-May, CHIPS Alliance announced the open sourcing of the SweRV Core™ EH2 and SweRV Core EL2 designed by Western Digital. These cores, as well as the earlier EH1, are now supported by Codasip’s SweRV Core Support Package which provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip. But what is SweRV Core EH2?
Codasip Presence at Upcoming Events: China Roadshow, DAC 2019, and RISC-V Workshop Zurich
Munich, Germany – May 6th, 2019 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, is going to be featured at three major industry events around the globe in the second quarter of 2019: China Roadshow 2019, Design Automation Conference in Las Vegas, and RISC-V Workshop in Zurich. “Getting Started with RISC-V” […]
Codasip Studio and Codasip CodeSpace 8.0 available
Codasip is pleased to announce the availability of Codasip Studio and Codasip CodeSpace 8.0.0. Key features of this release: Introduction of a new Codasip Bus Protocol (CPB) Integration of LLDB Integration of OpenOCD Full changelog is available at: https://support.codasip.com/downloads/changelog/ The release is available in the Downloads section of our website: https://support.codasip.com/downloads/software/ Any feedback on this […]