Bring your truly unique processing application to life, quickly and easily, using Codasip’s highly automated processor IP generation technology. Our comprehensive design and customization toolsuite, Codasip Studio, helps you do in days what would otherwise take months using traditional methods.
Rapid IP exploration and refinement
Codasip Studio manages every aspect of your processor design project, from implementation to verification, programming, emulation, and debug. Based on the Eclipse environment, it is well-known and easily used by both HW and SW development teams. Advanced profiling and debug make it easy to understand your design and get exactly the results you desire.
Codasip offers two possible paths to create your unique processor architecture.
1. RISC-V Cores Tailoring
Start with one of our proven RISC-V cores as the base for your design. Our cores are supplied as modifiable CodAL™ models (Codasip’s processor-modeling language), and can be freely modified to get the exact processor you need. Codasip Studio will guide you through the process to ensure predictable and high-quality results.
2. From Scratch
Beginning with only the instruction-accurate (IA) model, you can generate a complete SDK for your processor and begin to explore and refine the optimal ISA for your design. Once you are happy with the results, add any cycle-accurate (CA) information (pipelining), and generate the complete processor implementation.
Industry-Standard Tools and Interfaces
Generated SDKs are based on leading open-source tools such as LLVM and GNU. This means that our solutions can take advantage of the rapid pace of improvement in the underlying technology, our customers are able to integrate their own enhancements into the generated tools, and the whole toolsuite can be easily transferred when needed.
Clean High-performance RTL
Generated RTL is optimized for leading domain-specific ICs and FPGA synthesis tools to ensure high-quality results. Our compiler generator contains innovative proprietary improvements, and the resultant benchmarks show that our automatically generated RTL is equal to, or higher performance than, hand-coded implementations.
Also, the RTL produced by Codasip Studio is clean and human-readable.
Our strong verification methodology combines a standardized approach, simulation, and static checking for reliable results. Codasip Studio automatically generates UVM environment that allows the generated RTL for your processor to be checked against your instruction-accurate reference model. Multiple model formats are available to ensure that at each step of the verification, you have the best trade-off between viability and performance.
“Codasip gave us the flexibility to create a truly unique RISC-V processor, specific to our needs. This saved us the effort to build our own processor from scratch and allowed us to focus on other critical areas of the product development.”Ty Garibay, VP of Hardware Engineering, Mythic