Do you want to be a RISC-V leader, not a follower?
THEN DESIGN FOR DIFFERENTIATION!
RISC-V offers the opportunity for new companies to disrupt the industry. Codasip’s customized solutions open up the potential for your creativity: Design For Differentiation with Codasip Studio and RISC-V cores. Codasip has already shipped an estimated 2bn cores.
Find out how your designs could benefit, see us at RISC-V Summit 2021!
Our talks
Ron Black, CEO
KEYNOTE
Scaling is Failing
Wednesday, December 8, 2:15pm – 2:25pm
After 50 years of driving semiconductor economics, the underlying “semiconductor laws” are failing at a time when advanced manufacturing is becoming prohibitively expensive. Photonics and alternate materials such as carbon nanotubes have been suggested as alternatives but the only short-term option is to match hardware to computational workload through heterogeneous computing. RISC-V’s modularity combined with design automation provides a foundation for creating novel processors and domain-specific accelerators. Industry must adapt or die!
Zdeněk Přikryl, CTO, Codasip
Demo
10 Minute RISC-V Custom Instructions
Monday, December 6, 3:05pm – 3:15pm
Codasip will show how you can use the Studio tool to create a custom RISC-V instruction, toolchain, simulator and debug it in just 10 minutes
David Luo, Mythic & Zdeněk Přikryl, Codasip
Lightning Talk
Using and Extending RISC-V in an Analog Matrix Processor for Neural Networks
Monday, December 6, 4:15pm – 4:25pm
A characteristic of the RISC-V ISA is its provision for custom extensions enabling the ISA to be tailored to the needs of a particular workload. Mythic has developed the M1076 Analog Matrix Processor (AMP) chip for implementing neural networks for applications such as intelligent camera systems, robotics, etc. The AMP includes a configurable array of tiles. Each tile consists of a large analog compute engine, which stores the neural network weights, a local SRAM memory for data being passed between the neural network nodes, an SIMD unit for processing operations not handled by the analog compute array, and a RISC-V processor for controlling the sequencing and operation of the tile. The RISC-V processor is described in an architectural language which means that it is possible to extend the core by describing additional instructions and automatically generating the SDK, RTL and verification environment. This paper describes the AMP architecture and the requirements for extending the RISC-V processor to meet the sequencing and control needs. The paper describes how custom instructions were chosen and implemented in the architecture description language rather than RTL
Imen Baili, Menta & Zdeněk Přikryl, Codasip
Hosted by DAC
Updating RISC-V microarchitecture in the field through Menta co-extended cores and Codasip Studio
Wednesday, December 6, 5:00pm – 6:00pm
This paper describes how Menta and Codasip enable customers to extend processors in systems on chip (SoC) after they have been manufactured.
The RISC-V ISA is modular and allows custom instructions. Codasip Studio can be used to extend a Codasip core using custom instructions with the necessary additional logic implemented in the datapath. The joint solution allows this extra logic to be implemented in the field using an eFPGA co-extended core.
Specialized user interface tools to program the eFPGA matrix and to set up the RISC-V application programmable parameters, will be provided within a complete and optimized software solution.
Forrest Pickett, FAE, Codasip
Booth DEMO
Codasip Application Processor Evaluation Platform
Wednesday, December 6
The demo shows a linux prompt and the ability to control a simple LCD screen on the FPGA board.
Forrest Pickett, FAE, Codasip
Booth DEMO
Codasip Embedded Processor Evaluation Platform
Wednesday, December 6
The demo shows GPIO blinking lights, QSPI being written, I2C measuring the temperature, and two benchmarks running.
Zdeněk Přikryl, Codasip & Imen Baili, Menta
Hosted by DAC, booth #1346
Extending RISC-V Cores in the Field
Monday, December 6, 1:00 – 2:00pm
Tuesday, December 7, 2:00 – 3:00pm
Wednesday, December 8, 3:00 – 4:00pm
Our Booth
Find us at booth B10 in the Platinum Sponsor section in the Moscone West Hall.
How to get there
Please note that RISC-V Summit 2021 is co-located with 58th DAC.
Official announcement