Codasip, the leader in processor design automation and RISC-V processor IP, announces that its Lead IP Architect Tariq Kurd has been chosen by the RISC-V Board of Directors to receive the RISC-V Technical Contributor Award.
Tariq Kurd currently chairs the Code Size Reduction Task Group, which will develop a holistic solution to reducing code size, making RISC-V more competitive with existing embedded core architectures. Priority is given to small, embedded cores which often have very constrained memory sizes, but larger, higher-performance cores will also benefit from reduced code size. The work of the Code Size Reduction Task Group is close to ratification.
In addition, Tariq Kurd is the Chair of the Task Group for Zfinx, which has been ratified. The work of the Zfinx Task Group is related to sharing floating point and integer registers to save area and reduce context switch time. He has also contributed to the ratified ePMP specification for memory access and execution prevention on machine mode.
At Codasip, Tariq Kurd is the Lead IP Architect, mainly focusing on the application core family but also on other aspects such as functional safety, security, and the specification of next-generation Codasip’s processor IP, including processors based on the award-winning L31. Before joining Codasip, he was with Huawei and there led the company’s efforts to migrate processors to RISC-V. He received a RISC-V Community Contributor Award in 2021.
Tariq Kurd commented: “The work of the Code Size Task Group will help RISC-V catch up with other embedded architectures and I am currently focused on getting its work ready for ratification in early 2023. What will be my next contribution to the RISC-V Community, I do not know yet, but I have several ideas for making RISC-V even more competitive with other architectures.”
