Codasip L110 delivers up to 50% improvements in performance per watt and 20% smaller code size compared to similar cores in the market
Munich, Germany, June 4, 2024 – Codasip, the leader in RISC-V Custom Compute, has introduced a new low-power embedded processor core, and the next generation of processor design automation toolset Codasip Studio. Codasip L110 delivers best-in-class performance for power-sensitive applications. In addition, customers can easily add their unique customizations for unprecedented application-specific PPA (Power, Performance, and Area) improvements. A new level of customization in Codasip Studio Fusion, Bounded Customization, lets customers achieve a fast time to market for high-quality, fully verified RISC-V cores. The core can be extended with new instructions without risk because the functionality of the baseline core is guaranteed. A new verification framework substantially simplifies the verification of custom instructions.
“Customization allows designers to introduce new instructions specific to their software workload and significantly improve PPA,” comments Brett Cline, chief commercial officer at Codasip. “Our new core offers best-in-class performance for small-area and low-power applications accompanied by new possibilities for easy and quick customization with no risk to the core functionality. We offer all this in a flexible business model that will not cost you an arm and a leg.”
New Codasip L110 RISC-V CPU core changes the game
Codasip L110 delivers up to 50% improvements in performance per watt and 20% smaller code size compared to similar cores in the market. The core offers extensive configurability, allowing different area/performance trade-off levels, and support for standard RISC V code-size extensions. Additionally, the L110 is fully customizable allowing designers to extend the processor to achieve massive PPA improvements to differentiate their products. Designed by the Codasip team using Codasip Studio Fusion, L110 is ideal for small-area, low-power applications, such as state machine replacements, sensor controllers, and IoT edge.
Codasip Studio Fusion introduces unique processor design and verification features with unparalleled productivity
For years, Codasip Studio has been the toolset to generate both the RTL and the software development tools from a single processor model. The new version, Codasip Studio Fusion, improves this fundamental capability and adds a segmentation layer. Customers can configure the core from set options, create custom instructions within set bounds, or design freely. The tools automatically generate an SDK (Software Development Toolkit) including a compiler, simulation models, debugger, and profiler, and an HDK (Hardware Development Kit) including RTL (Register Transfer Level), a verification framework, and more.
The latest version also introduces more design automation to make processor design even easier and faster. New design constructs allow for fusing the processor’s architectural and microarchitectural description. The toolset can also automatically convert declarative descriptions of common processor aspects into low-level logic.
The benefits of the Codasip Studio Fusion toolset are all reflected in the new L110 core, which can be used as a pre-verified starting point to achieve the right level of customization. For customers in need of a starting point with higher performance, Codasip offers other options such as the 64-bit RISC-V application core A730.
