New approach to safe and secure custom compute
RISC-V Summit, San Jose – Codasip, the leader in processor design automation and RISC-V processor IP, today launched SecuRISC5, a Codasip initiative to provide its customers with safe and secure custom compute using highly verified reference designs combining Codasip IP and third-party technology. Codasip Labs, launched recently by Codasip, will play a central role in identifying opportunities where SecuRISC5 should focus its attention and will also act as the hub, coordinating pan-industry collaboration.
Following the recent acquisition of Cerberus Security Labs, Codasip is accelerating security developments for its RISC-V processor IP and plans to make security reference designs available in 2023. Because a truly secure system cannot be developed in isolation, Codasip is working with partners to deliver a complete and secure RISC-V ecosystem.
Jamie Broome, Vice President of Automotive and Products, Codasip, commented: “Security is the ‘feature’ that people often fail to see the value in, but everyone knows they need. Another important aspect is that without security, there is no safety, and we are therefore adopting a holistic approach. We will help our customers integrate RISC-V safety and security by providing more than secure cores.”
“It’s great to see Codasip take the initiative to boost security of RISC-V devices; if security is not tackled properly, it’s a potential threat to the wider adoption of RISC-V. We will be working closely with Codasip and other ecosystem partners to provide developers the opportunity to build and test out their secure concepts using Intel® Pathfinder for RISC-V2 running in a trusted FPGA environment,” said Vijay Krishnan, General Manager, RISC-V Ventures at Intel.
John Hartley, Chief Commercial Officer of Crypto Quantique, said: “Crypto Quantique and Codasip share a mission of enabling seamless end-to-end security for RISC-V. For a device to be fully secure, security must be considered from the start of a development project. It also needs to be scalable and future-proof to ensure systems are protected from all threats for the lifecycle of the device. The only way to manage this is by working together as an industry to ensure security by design. We welcome this initiative from Codasip.”
RISC-V offers an ideal platform to develop the widest range of systems for all types of secure applications and functions – particularly for domain-specific designs which struggle to get the custom solution or the necessary support from proprietary ISAs. RISC-V is increasingly being implemented in security systems1 and Codasip is active in the RISC-V standards processes. The SecuRISC5 initiative will build on the work of the RISC-V International Working Groups and will implement new standards as they are ratified.
Codasip RISC-V processors are also supported by a secure-boot function from Veridify.
Ron Black, Codasip CEO, will be talking about the fundamental disconnect in safety and security during his spotlight presentation to the #RISCVSummit in San Jose on 13 December 2022. Technology previews of secure IP features and end-to-end IoT security will be showcased at Codasip’s booth.
1Recent examples include the open-source RISC-V root-of-trust project OpenTitan and the Caliptra security architecture, mandated by Google, Microsoft, AMD, and Nvidia for data center security.
2Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. No product or component can be absolutely secure.