RISC-V dual lock-step implementation for safety and security applications
Tuesday, December 13, 3:30pm – 3:40pm
In this session, we demonstrate how a secure dual-core lockstep processor can be used to detect and trap faults injected at the hardware level, no matter if that fault was caused by a system malfunction or a deliberate attack. To enable fault testing the design is annotated with smart fault injectors, a functionality that Codasip intends to provide to automate and aid the design of resilient compute systems. The smart fault injectors can be adapted to different fault models addressing the automotive functional safety ISO 26262:2018 as well as the automotive cybersecurity standard ISO/SAE 21434:2021. A proven method in other architectures, dual lockstep enables fault detection no matter what caused the fault.