RISC-V Processors


Codasip’s RISC-V-based processors (Bk) make use of the rich ecosystem of software and hardware enabled by the extensible, RISC-V Instruction-Set Architecture (ISA) Standard, while retaining the incredible flexibility of all Codasip-made cores.

“Codasip and RISC-V enable all the advantages of application tailoring, with the stability and predictability of off-the-shelf ARM designs, while delivering an order of magnitude performance improvement.”Derek Atkins, CTO, SecureRF

Proven processor implementations


Codasip currently offers the following base versions of the RISC-V architecture: with a 1-stage, 3-stage, 5-stage, and a 7-stage pipeline. All are fully compliant with the RISC-V specification and fully customizable.

  • Bk3 pipeline
  • Bk5 pipeline

In addition to the base processor implementation, Codasip provides standard support for optional instruction layers as defined by the current RISC-V specification.

 

Bk1

Bk3

Bk5

Bk5-64

Bk7

Base Integer ISA

RV32E

RV32E/I

RV32I

RV64I

RV64I

Compressed ISA

Optional

Optional

Optional

Optional

Optional

Single Precision “F”

Optional

Optional

Multiplication and Division “M”

Optional
(sequential)

Optional
(sequential/parallel)

Parallel

Parallel

Parallel

User mode (subset of privilege mode) “U”

Optional

Optional

Optional

Optional

Interrupt support

Jump predictor

JTAG Debug Support

Bk1

  • Base Integer ISA: RV32E
  • Compressed ISA: Optional
  • Single Precision “F”
  • Multiplication and Division “M”: Optional (sequential)
  • User mode (subset of privilege mode) “U”
  • Interrupt support
  • Jump predictor
  • JTAG Debug Support

Bk3

  • Base Integer ISA: RV32E/I
  • Compressed ISA: Optional
  • Single Precision “F”
  • Multiplication and Division “M”: Optional (sequential/parallel)
  • User mode (subset of privilege mode) “U”: Optional
  • Interrupt support
  • Jump predictor
  • JTAG Debug Support

Bk5

  • Base Integer ISA: RV32I
  • Compressed ISA: Optional
  • Single Precision “F”: Optional
  • Multiplication and Division “M”: Parallel
  • User mode (subset of privilege mode) “U”: Optional
  • Interrupt support
  • Jump predictor
  • JTAG Debug Support

Bk5-64

  • Base Integer ISA: RV64I
  • Compressed ISA: Optional
  • Single Precision “F”
  • Multiplication and Division “M”: Parallel
  • User mode (subset of privilege mode) “U”: Optional
  • Interrupt support
  • Jump predictor
  • JTAG Debug Support

Bk7

  • Base Integer ISA: RV64I
  • Compressed ISA: Optional
  • Single Precision “F”: Optional
  • Multiplication and Division “M”: Parallel
  • User mode (subset of privilege mode) “U”: Optional
  • Interrupt support
  • Jump predictor
  • JTAG Debug Support

Completely customizable


All Codasip Bk cores are fully customizable to the needs of your design. Changes can be made by Codasip as part of the standard deliverable, or by your own developers using our unique IP Generation Toolkit (Codasip Studio).

Need a single-cycle MAC, specialized crypto functions, or support for non-standard data types? No problem. Better yet, thanks to the extensible nature of the RISC-V ISA, all tailored cores remain RISC-V compliant, allowing you to use the growing SW Ecosystem.

State-of-the-art Commercial SDK Support


The Bk cores are supported by industry-leading SDK that is based on LLVM, GNU and other open standards, but is optimized for your unique processor configuration and backed by Codasip’s comprehensive support.

State-of-the-art Commercial SDK Support


The Bk cores are supported by industry-leading SDK that is based on LLVM, GNU and other open standards, but is optimized for your unique processor configuration and backed by Codasip’s comprehensive support.

Open, Extensible, Industry-supported


Codasip is proud to be a founding member of the RISC-V Foundation, joining industry leaders such as Google, Oracle, HP, AMD, Nvidia, and many others.

The power of RISC-V is that it defines an ISA that helps a healthy HW and SW ecosystems develop, allowing each vendor to deliver their own unique value.