RISC-V Processors

The Bk series is Codasip’s own portfolio of RISC-V-based processors. RISC-V is an open, modern, extensible Instruction Set Architecture (ISA) that is becoming a new standard. Our processors built on RISC-V benefit from the rich ecosystem of software and hardware while retaining the incredible flexibility of all Codasip-made cores. Optionally, you can get the handy CodeSpace IDE with your new core.

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Proven processor implementations

Codasip currently offers the following base versions of the RISC-V architecture: with a 3-stage, 5-stage, and a 7-stage pipeline. All are fully compliant with the RISC-V specification, and fully customizable.

  • Bk3 pipeline

    Bk3 pipeline

  • Bk5 pipeline

    Bk5 pipeline

  • Bk7 pipeline

    Bk7 pipeline

In addition to the base processor implementation, Codasip provides standard support for optional instruction layers as defined by the current RISC-V specification.

 

Bk3

Bk5

Bk5-64

Bk7

Base Integer ISA

RV32E/I

RV32I

RV64I

RV64I

Compressed ISA “C”

Optional

Optional

Optional

Floating Point “F” Single Precision

Optional

Optional

Optional

Optional

Floating Point “D” Double Precision

Optional

Optional

Optional

Multiplication and Division “M”

Optional
(sequential/parallel)

Parallel

Parallel

Parallel

Privilege mode

M + U

M + U

M + U

M + S + U

Memory protection

Optional PMP
(8/16 regions)

Optional PMP
(8/16 regions)

Optional PMP
(8/16 regions)

MMU

Tightly coupled memory (instruction, data)

Optional

Optional

Optional

Coming soon

Interrupt support

Branch predictor

JTAG & RISC-V Debug Support (4pin/2pin)

Bk3

  • Base Integer ISA: RV32E/I
  • Compressed ISA “C”: Optional
  • Floating Point “F” Single Precision: Optional
  • Floating Point “D” Double Precision: N/A
  • Multiplication and Division “M”: Optional (sequential/parallel)
  • Privilege mode: M + U
  • Memory protection: Optional PMP (8/16 regions)
  • Tightly coupled memory (instruction, data): Optional
  • Interrupt support
  • Branch predictor
  • JTAG & RISC-V Debug Support (4pin/2pin)

Bk5

  • Base Integer ISA: RV32I
  • Compressed ISA “C”: Optional
  • Floating Point “F” Single Precision: Optional
  • Floating Point “D” Double Precision: Optional
  • Multiplication and Division “M”: Parallel
  • Privilege mode: M + U
  • Memory protection: Optional PMP (8/16 regions)
  • Tightly coupled memory (instruction, data): Optional
  • Interrupt support
  • Branch predictor
  • JTAG & RISC-V Debug Support (4pin/2pin)

Bk5-64

  • Base Integer ISA: RV64I
  • Compressed ISA “C”: Optional
  • Floating Point “F” Single Precision: Optional
  • Floating Point “D” Double Precision: Optional
  • Multiplication and Division “M”: Parallel
  • Privilege mode: M + U
  • Memory protection: Optional PMP (8/16 regions)
  • Tightly coupled memory (instruction, data): Optional
  • Interrupt support
  • Branch predictor
  • JTAG & RISC-V Debug Support (4pin/2pin)

Bk7

  • Base Integer ISA: RV64I
  • Compressed ISA “C”
  • Floating Point “F” Single Precision: Optional
  • Floating Point “D” Double Precision: Optional
  • Multiplication and Division “M”: Parallel
  • Privilege mode: M + S + U
  • Memory protection: MMU
  • Tightly coupled memory (instruction, data): Coming soon
  • Interrupt support
  • Branch predictor
  • JTAG & RISC-V Debug Support (4pin/2pin)

Completely customizable

All Codasip Bk cores are fully customizable to the needs of your design. Changes can be made by Codasip as part of the standard deliverable, or by your own developers using our unique, easy-to-use toolsuite Codasip Studio.

Need a single-cycle MAC, specialized crypto functions, or support for non-standard data types? No problem. And thanks to the extensible nature of the RISC-V ISA, all tailored cores remain RISC-V-compliant, allowing you to use the growing software ecosystem.

State-of-the-art Commercial SDK Support

The Bk cores are supported by industry-leading SDK that is based on LLVM, GNU and other open standards, but is optimized for your unique processor configuration and backed by Codasip’s professional support.

Codasip CodeSpace

To write software for your new core, you can use Codasip CodeSpace. This firmware development environment is based on the open Eclipse framework and can be purchased separately. It is a convenient standalone tool for code editing, compiling, profiling, and debugging.

State-of-the-art Commercial SDK Support

The Bk cores are supported by industry-leading SDK that is based on LLVM, GNU and other open standards, but is optimized for your unique processor configuration and backed by Codasip’s comprehensive support.

Open, Extensible, Industry-supported

Codasip is proud to be a founding member of the RISC-V Foundation, joining industry leaders such as Google, Oracle, HP, AMD, Nvidia, and many others.

The power of RISC-V ISA helps the development of a healthy, open HW and SW ecosystem, fosters collaboration and innovation, and allows each vendor to deliver their own unique value both to the shared ecosystem and to the market.

“Codasip and RISC-V enable all the advantages of application tailoring, with the stability and predictability of off-the-shelf ARM designs, while delivering an order of magnitude performance improvement.”Derek Atkins, CTO, SecureRF

Get your Bk processor

Our worldwide Sales team will be happy to help and recommend the best RISC-V core to fit your needs. Get your quote today!

Contact our Sales team