Codasip’s own portfolio of off-the-shelf processor cores is built on RISC-V, a modern open Instruction Set Architecture (ISA). The processors benefit from the rich ecosystem of software and hardware while retaining incredible flexibility. They can be deployed as-is and you will get the handy CodeSpace IDE with your new core. Alternatively, you can use the IP as a quick starting point for your own custom design using our unique, highly automatized Codasip Studio toolset.

Proven processor implementations


Codasip currently offers three processor families:
Small and energy-efficient Low Power Embedded cores,
more powerful High Performance Embedded cores,
and the most advanced Application cores able to run Linux.

Watch video introduction to the Application cores

In each of the families, you can choose from a number of series based on the microarchitecture complexity.

Codasip processor families and series

All Codasip designs are fully compliant with the RISC-V specification and fully customizable.

Processor Portfolio


All cores
  • Standard RISC-V debug
  • JTAG (4pin/2pin)
  • Compressed instructions
  • AMBA buses
Low Power Embedded
  • 32-bit
  • Up to 128 interrupts
High Performance Embedded
  • 64-bit
  • 32-bit with performance-boosting features
  • Up to 256 interrupts
Application
  • 64-bit
  • Floating point unit
  • Linux support:
    • RV64GC ISA
    • Atomic instructions
    • Memory management unit
    • Supervisor privilege mode
7 series
  • 7–9-stage pipeline
  • IMC instruction set
  • 32 registers
  • Branch predictor
  • Parallel multiplier
Codasip A70X
Codasip A70XP
Codasip A70X-MP
Codasip A70XP-MP
5 series
  • 5-stage pipeline
  • IMC instruction set
  • 32 registers
  • Branch predictor
  • Parallel multiplier
Codasip L50
Codasip L50F
Codasip H50X
Codasip H50XF
3 series
  • 3–4-stage pipeline
  • IMC instruction set
  • 32 registers
  • Parallel multiplier
Codasip L30
Codasip L30F
1 series
  • 3-stage pipeline
  • EMC instruction set
  • 16 registers
  • Sequential multiplier
Codasip L10
X = 64-bit, F = Floating Point Unit, P = RISC-V P Packed SIMD Extension, MP = Multiprocessing

 All cores

Low Power
Embedded

High Performance
Embedded

 Application

  • Standard RISC-V debug
  • JTAG (4pin/2pin)
  • Compressed instructions
  • AMBA buses
  • 32-bit
  • Up to 128 interrupts
  • 64-bit
  • 32-bit with performance-boosting features
  • Up to 256 interrupts
  • 64-bit
  • Floating point unit
  • Linux support:
    • RV64GC ISA
    • Atomic instructions
    • Supervisor mode
    • MMU

7 series

  • 7–9-stage pipeline
  • IMC instruction set
  • 32 registers
  • Branch predictor
  • Parallel multiplier

 

 

Codasip A70X
Codasip A70XP
Codasip A70X-MP
Codasip A70XP-MP

5 series

  • 5-stage pipeline
  • IMC instruction set
  • 32 registers
  • Branch predictor
  • Parallel multiplier

Codasip L50
Codasip L50F

Codasip H50X
Codasip H50XF

 

3 series

  • 3–4-stage pipeline
  • IMC instruction set
  • 32 registers
  • Parallel multiplier

Codasip L30
Codasip L30F

 

 

1 series

  • 3-stage pipeline
  • EMC instruction set
  • 16 registers
  • Sequential multiplier

Codasip L10

 

 

X = 64-bit, F = Floating Point Unit, P = RISC-V P Packed SIMD Extension, MP = Multiprocessing

Complete customizability


All Codasip RISC-V Processors are fully customizable to the needs of your design. Changes can be made by Codasip, or by your own developers using our unique, easy-to-use toolsuite Codasip Studio.

Need a single-cycle MAC, specialized crypto functions, or support for non-standard data types? No problem. And thanks to the extensible nature of the RISC-V ISA, all tailored cores remain RISC-V-compliant, allowing you to use the growing software ecosystem.

State-of-the-art SDK


The Bk cores are supported by industry-leading SDK that is based on LLVM, GNU and other open standards, but is optimized for your unique processor configuration and backed by Codasip’s professional support.

To write software for your new core, you can use Codasip CodeSpace. This firmware development environment is based on the open Eclipse framework. It is a convenient standalone tool for code editing, compiling, profiling, and debugging. You will get a full 1-year license of Codasip CodeSpace by default with any of our cores.

Open, Extensible, Industry-supported


Codasip is proud to be a founding member of the RISC-V Foundation, joining industry leaders such as Google, Oracle, HP, AMD, Nvidia, and many others.

The power of the RISC-V architecture helps the development of a healthy, open HW and SW ecosystem, fosters collaboration and innovation, and allows each vendor to deliver their own unique value both to the shared ecosystem and to the market.

“Codasip and RISC-V enable all the advantages of application tailoring, with the stability and predictability of off-the-shelf ARM designs, while delivering an order of magnitude performance improvement.”Derek Atkins, CTO, SecureRF

Get your Codasip RISC-V Processor

Our worldwide Sales team will be happy to help and recommend the best RISC-V core to fit your needs. Get your quote today!